Abstract: Disclosed are circuits for dynamically configuring configurable micro-architectural circuits based on associated operating point indicators.

Abstract: An apparatus and method for efficiently processing denormals on a processor. For example, one embodiment of a processor comprises: a decoder to decode instructions of a program code sequence into mircooperations (uops); a control register to store one or more bits related to denormal processing; uop morphing circuitry to generate or select a first type of FP divide or square root uop when the one or more bits indicate no possibility of denormals and to generate or select a second type of FP divide or square root uop when the one or more bits indicate a possibility of denormals; and execution circuitry to execute the first type of FP divide or square root uop to generate a result or to execute the second type of FP divide or square root uop, handling any denormals in hardware, to generate the result.

Abstract: A power multiplexer (mux) circuit to switch between core and memory power supply rails. The power mux includes controllable variable resistance legs to adjust supply switch path resistances, for example, based on differences between the core and supply voltage rails.