Patents by Inventor Viraphol Chaiyakul

Viraphol Chaiyakul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Concurrent multiple-dimension word-addressable memory architecture
    Patent number: 8773944
    Abstract: An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Chihtung Chen, Inyup Kang, Viraphol Chaiyakul
  • CONCURRENT MULTIPLE-DIMENSION WORD-ADDRESSABLE MEMORY ARCHITECTURE
    Publication number: 20120134229
    Abstract: An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit ceils and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
    Type: Application
    Filed: February 8, 2012
    Publication date: May 31, 2012
    Inventors: Chihtung Chen, Inyup Kang, Viraphol Chaiyakul
  • Systems and methods for improving digital system simulation speed by clock phase gating
    Patent number: 8140316
    Abstract: An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: March 20, 2012
    Assignee: QUALCOMM, Incorporated
    Inventors: Tauseef Kazi, Haobo Yu, Lukai Cai, Mahesh Sridharan, Viraphol Chaiyakul
  • Concurrent multiple-dimension word-addressable memory architecture
    Patent number: 8120989
    Abstract: An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: February 21, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Chihtung Chen, Inyup Kang, Viraphol Chaiyakul
  • SYSTEMS AND METHODS FOR IMPROVING DIGITAL SYSTEM SIMULATION SPEED BY CLOCK PHASE GATING
    Publication number: 20100114551
    Abstract: An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 6, 2010
    Applicant: QUALCOMM Incorporated
    Inventors: Tauseef Kazi, Haobo Yu, Lukai Cai, Mahesh Sridharan, Viraphol Chaiyakul
  • Concurrent Multiple-Dimension Word-Addressable Memory Architecture
    Publication number: 20080316835
    Abstract: An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
    Type: Application
    Filed: June 25, 2007
    Publication date: December 25, 2008
    Inventors: Chihtung Chen, Inyup Kang, Viraphol Chaiyakul