Patents by Inventor Viren C. Patel

Viren C. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6232186
    Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance Cgd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: May 15, 2001
    Assignee: STMicroelectronics, Inc.
    Inventor: Viren C. Patel
  • Patent number: 6207508
    Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance Cgd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: March 27, 2001
    Assignee: STMicroelectronics, Inc.
    Inventor: Viren C. Patel
  • Patent number: 6087697
    Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance C.sub.gd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: July 11, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Viren C. Patel
  • Patent number: 6040617
    Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.
    Type: Grant
    Filed: December 22, 1992
    Date of Patent: March 21, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Viren C. Patel
  • Patent number: 5977588
    Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance C.sub.gd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: November 2, 1999
    Assignee: STMicroelectronics, Inc.
    Inventor: Viren C. Patel
  • Patent number: 5543655
    Abstract: The present invention is directed to an improved base-collector junction transistor structure capable of higher junction breakdown voltages and lower junction capacitances than bipolar transistors of the prior art. A narrow trench is used to positively affect junction breakdown voltage and junction capacitance. The trench allows the beneficial characteristics of both depletion ring and mesa structures to be utilized. Depletion zone profiles that negatively affect junction breakdown voltage are minimized by using the trench and a depletion enhancing channel.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: August 6, 1996
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Viren C. Patel