Patents by Inventor Virendra R. Jadhav

Virendra R. Jadhav has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11244917
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11171102
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 11094657
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity
    Patent number: 10699972
    Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190326242
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190326243
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 10403590
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 10396051
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20190157230
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • FLAT LAMINATE, SYMMETRICAL TEST STRUCTURES AND METHOD OF USE TO GAUGE WHITE BUMP SENSITIVITY
    Publication number: 20180082912
    Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 22, 2018
    Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
  • Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity
    Patent number: 9899279
    Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20170170135
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: February 28, 2017
    Publication date: June 15, 2017
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20170133338
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 11, 2017
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9640501
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9472520
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Determining magnitude of compressive loading
    Patent number: 9366591
    Abstract: An apparatus for determining a magnitude of a compressive load applied to a piston including a compliant film disposed between first and second elements is provided. The apparatus includes a first part movable with the first element in a movement direction along which the magnitude of the compressive load is to be determined, a second part movable with the second element in the movement direction and a sensor to measure a distance between the first and second parts in the movement direction, the measured distance being related to a deformation of the compliant film as the compressive load is applied.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: June 14, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul F. Bodenweber, Virendra R. Jadhav, Steven P. Ostrander, Kamal K. Sikka, Jiantao Zheng, Jeffrey A. Zitz
  • Multilayer pillar for reduced stress interconnect and method of making same
    Patent number: 9111816
    Abstract: A multi-layer pillar is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: August 18, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME
    Publication number: 20150054152
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate.
    Type: Application
    Filed: October 29, 2014
    Publication date: February 26, 2015
    Inventors: Virendra R. JADHAV, Krystyna W. SEMKOW, Kamalesh K. SRIVASTAVA, Brian R. SUNDLOF
  • Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity
    Patent number: 8957531
    Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad
  • FLAT LAMINATE, SYMMETRICAL TEST STRUCTURES AND METHOD OF USE TO GAUGE WHITE BUMP SENSITIVITY
    Publication number: 20150036716
    Abstract: A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: William E. Bernier, Timothy H. Daubenspeck, Virendra R. Jadhav, Valerie A. Oberson, David L. Questad