Patents by Inventor Virendra V. S. Rana

Virendra V. S. Rana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8569650
    Abstract: Embodiments of the present invention generally provide methods and apparatus for material removal using lasers in the fabrication of solar cells. In one embodiment, an apparatus is provided that removes portions of a dielectric layer deposited on a solar cell substrate according to a desired pattern. In certain embodiments, methods for removing a portion of a material via a laser without damaging the underlying substrate are provided. In one embodiment, the intensity profile of the beam is adjusted so that the difference between the maximum and minimum intensity within a spot formed on a substrate surface is reduced to an optimum range. In one example, the substrate is positioned such that the peak intensity at the center versus the periphery of the substrate is lowered. In one embodiment, the pulse energy is improved to provide thermal stress and physical lift-off of a desired portion of a dielectric layer.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: October 29, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Zhenhua Zhang, Virendra V. S. Rana, Vinay K. Shah, Chris Eberspacher
  • Patent number: 8372753
    Abstract: A method and apparatus for cleaning layers of solar cell substrates is disclosed. The substrate is exposed to a reactive gas that may comprise neutral radicals comprising nitrogen and fluorine, or that may comprise anhydrous HF and water, alcohol, or a mixture of water and alcohol. The reactive gas may further comprise a carrier gas. The reactive gas etches the solar cell substrate surface, removing oxygen and other impurities. When exposed to the neutral radicals, the substrate grows a thin film containing ammonium hexafluorosilicate, which is subsequently removed by heat treatment.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: February 12, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V S Rana, Michael P. Stewart
  • Patent number: 8283199
    Abstract: Embodiments of the present invention generally provide methods for forming conductive structures on the surfaces of a solar cell. In one embodiment, conductive structures are formed on the front surface of a solar cell by depositing a sacrificial polymer layer, forming patterned lines in the sacrificial polymer via a fluid jet, depositing metal layers over the front surface of the solar cell, and performing lift off of the metal layers deposited over the sacrificial polymer by dissolving the sacrificial polymer with a water based solvent.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: October 9, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V. S. Rana, Chris Eberspacher, Karl J. Armstrong, Nety M. Krishna
  • Patent number: 8258426
    Abstract: Embodiments of the present invention generally provide methods and apparatus for material removal using lasers in the fabrication of solar cells. In one embodiment, an apparatus is provided that precisely removes portions of a dielectric layer deposited on a solar cell substrate according to a desired pattern and deposits a conductive layer over the patterned dielectric layer. In one embodiment, the apparatus also removes portions of the conductive layer in a desired pattern. In certain embodiments, methods for removing a portion of a material via a laser without damaging the underlying substrate are provided. In one embodiment, the intensity profile of the beam is adjusted so that the difference between the maximum and minimum intensity within a spot formed on a substrate surface is reduced to an optimum range. In one example, the substrate is positioned such that the peak intensity at the center versus the periphery of the substrate is lowered.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: September 4, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Zhenhua Zhang, Virendra V. S. Rana, Vinay K. Shah, Chris Eberspacher
  • Patent number: 8173473
    Abstract: An apparatus and method for processing the solar cell substrates is provided. In one embodiment, a laser firing chamber for processing solar cell substrates placed in a carrier, comprising a laser module located at a side of the carrier, the laser module being adapted to generate and direct multiple laser beams over an entire surface of a plurality of solar cell substrates, and a transport adapted to convey the carrier through an outputting region of the laser beams.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: May 8, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Derek Aqui, Steven M. Zuniga, Venkateswaran Subbaraman, Kirk Liebscher, John Alexander, Zhenhua Zhang, Virendra V. S. Rana
  • Patent number: 8088675
    Abstract: A method for obtaining a desired dopant profile of an emitter for a solar cell which includes depositing a first amorphous silicon layer having a first doping level over an upper surface of the crystalline silicon substrate, depositing a second amorphous silicon layer having a second doping level on the first amorphous silicon layer, and heating the crystalline silicon substrate and the first and second amorphous silicon layers to a temperature sufficient to cause solid phase epitaxial crystallization of the first and second amorphous silicon layers, such that the first and second amorphous silicon layers, after heating, have the same grain structure and crystal orientation as the underlying crystalline silicon substrate.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: January 3, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V. S. Rana, Robert Z. Bachrach
  • Publication number: 20100261302
    Abstract: A method and apparatus for cleaning layers of solar cell substrates is disclosed. The substrate is exposed to a reactive gas that may comprise neutral radicals comprising nitrogen and fluorine, or that may comprise anhydrous HF and water, alcohol, or a mixture of water and alcohol. The reactive gas may further comprise a carrier gas. The reactive gas etches the solar cell substrate surface, removing oxygen and other impurities. When exposed to the neutral radicals, the substrate grows a thin film containing ammonium hexafluorosilicate, which is subsequently removed by heat treatment.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 14, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: VIRENDRA V. S. RANA, Michael P. Stewart
  • Patent number: 7749917
    Abstract: A method and apparatus for cleaning layers of solar cell substrates is disclosed. The substrate is exposed to a reactive gas that may comprise neutral radicals comprising nitrogen and fluorine, or that may comprise anhydrous HF and water, alcohol, or a mixture of water and alcohol. The reactive gas may further comprise a carrier gas. The reactive gas etches the solar cell substrate surface, removing oxygen and other impurities. When exposed to the neutral radicals, the substrate grows a thin film containing ammonium hexafluorosilicate, which is subsequently removed by heat treatment.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: July 6, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V S Rana, Michael P. Stewart
  • Patent number: 6374770
    Abstract: A chemical vapor deposition system that includes a housing configured to form a processing chamber, a substrate holder configured to hold a substrate within the processing chamber, a gas distribution system configured to introduce gases into the processing chamber, a plasma generation system configured to form a plasma within the processing chamber, a processor operatively coupled to control the gas distribution system and the plasma generation system, and a computer-readable memory coupled to the processor that stores a computer-readable program which directs the operation of the chemical vapor deposition system.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: April 23, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Peter W. Lee, Stuardo Robles, Anand Gupta, Virendra V. S. Rana, Amrita Verma
  • Patent number: 6289843
    Abstract: A method and apparatus for depositing a layer having improved film quality at an interface. The method includes the steps of introducing an inert gas into a processing chamber and forming a plasma from the inert gas by applying RF power to the chamber at a selected rate of increase. After RF power has reached full power, a process gas including a reactant gas is introduced to deposit the layer. In a preferred embodiment, the reactant gas is tetraethoxysilane. In another preferred embodiment, the process gas further includes fluorine.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: September 18, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Virendra V. S. Rana, Amrita Verma, Mohan K. Bhan, Sudhakar Subrahmanyam
  • Patent number: 6291028
    Abstract: A method and apparatus for depositing a layer having improved film quality at an interface. The method includes the steps of introducing an inert gas into a processing chamber and forming a plasma from the inert gas by applying RF power to the chamber at a selected rate of increase. After RF power has reached full power, a process gas including a reactant gas is introduced to deposit the layer. In a preferred embodiment, the reactant gas is tetraethoxysilane. In another preferred embodiment, the process gas further includes fluorine.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 18, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Virendra V. S. Rana, Amrita Verma, Mohan K. Bhan, Sudhakar Subrahmanyam
  • Patent number: 6191026
    Abstract: A semiconductor manufacturing process with improved gap fill capabilities is provided by a three step process of FSG deposition/etchback/FSG deposition. A first layer of FSG is partially deposited over a metal layer. An argon sputter etchback step is then carried out to etch out excess deposition material. Finally, a second layer of FSG is deposited to complete the gap fill process.
    Type: Grant
    Filed: January 9, 1996
    Date of Patent: February 20, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Virendra V. S. Rana, Andrew Conners, Anand Gupta, Xin Guo, Soonil Hong
  • Patent number: 6190233
    Abstract: A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: February 20, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Soonil Hong, Choon Kun Ryu, Michael P. Nault, Kaushal K. Singh, Anthony Lam, Virendra V. S. Rana, Andrew Conners
  • Patent number: 6121163
    Abstract: A method and apparatus for depositing a layer having improved film quality at an interface. The method includes the steps of introducing an inert gas into a processing chamber and forming a plasma from the inert gas by applying RF power to the chamber at a selected rate of increase. After RF power has reached full power, a process gas including a reactant gas is introduced to deposit the layer. In a preferred embodiment, the reactant gas is tetraethoxysilane. In another preferred embodiment, the process gas further includes fluorine.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: September 19, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Anand Gupta, Virendra V. S. Rana, Amrita Verma, Mohan K. Bhan, Sudhakar Subrahmanyam
  • Patent number: 6103601
    Abstract: A fluorine-doped silicate glass (FSG) layer having a low dielectric constant and a method of forming such an insulating layer is described. The FSG layer is treated with a post-treatment step to make the layer resistant to moisture absorption and outgassing of fluorine atoms. In one embodiment, the post-treatment step includes forming a thin, undoped silicate glass layer on top of the FSG layer, and in another embodiment, the stability of the FSG film is increased by a post-treatment plasma step.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: August 15, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Peter W. Lee, Stuardo Robles, Anand Gupta, Virendra V. S. Rana, Amrita Verma
  • Patent number: 5990000
    Abstract: A method and an apparatus for depositing a dielectric layer to fill in a gap between adjacent metal lines. In preferred embodiments of the method, a first dielectric layer is deposited over the lines and subsequently etched using both chemical and physical etchback steps. After the etchback steps are completed, a second dielectric layer is deposited over the first dielectric layer to fill in the gap.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: November 23, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Soonil Hong, Choon Kun Ryu, Michael P. Nault, Kaushal K. Singh, Anthony Lam, Virendra V. S. Rana, Andrew Conners
  • Patent number: 5944899
    Abstract: An apparatus and method are provided for an inductively coupled plasma within a reactor for processing semiconductor wafers or workpieces. A gas distribution system having an annular passage formed between the chamber walls and quartz dome uniformly inlet gases over the wafer. The system of the present invention provides an increased etch rate with high selectively and anistropy.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: August 31, 1999
    Assignee: Applied Materials, Inc.
    Inventors: Xin Sheng Guo, Virendra V. S. Rana
  • Patent number: 5827785
    Abstract: A method and apparatus for improving film stability of a halogen-doped silicon oxide layer. The method includes the step of introducing a process gas including a first halogen source and a second halogen source, different from the first halogen source, into a deposition chamber along with silicon and oxygen sources. A plasma is then formed from the process gas to deposit a halogen-doped layer over a substrate disposed in the chamber. It is believed that the introduction of the additional halogen source enhances the etching effect of the film. The enhanced etching component of the film deposition improves the film's gap-fill capabilities and helps stabilizes the film. In a preferred embodiment, the halogen-doped film is a fluorosilicate glass film, SiF.sub.4 is employed as the first halogen source, TEOS is employed as a source of silicon and the second halogen source is either F.sub.2 or NF.sub.3.
    Type: Grant
    Filed: October 24, 1996
    Date of Patent: October 27, 1998
    Assignee: Applied Materials, Inc.
    Inventors: Mohan Krishan Bhan, Sudhakar Subrahmanyam, Anand Gupta, Virendra V. S. Rana
  • Patent number: 5421401
    Abstract: A compound clamp ring secures a semiconductor wafer having a wafer flat portion to a wafer pedestal during wafer processing while maintaining a continuous seal between the wafer edges and the wafer pedestal to prevent leakage of coolant gases circulated at the backside of the wafer into the process environment. The clamp ring has an annular wafer clamp surface adapted to press a round portion of the wafer into sealing abutment with the wafer pedestal. A cavity formed in the clamp ring securely receives a comb-like array of resilient flexures that are adapted to apply a yieldable bias to the flat portion of the wafer to complete the seal between the wafer and the pedestal at the flat portion of the wafer; and encloses the flexures to shield the flexures from process gases.
    Type: Grant
    Filed: January 25, 1994
    Date of Patent: June 6, 1995
    Assignee: Applied Materials, Inc.
    Inventors: Semyon Sherstinsky, Mei Chang, Charles C. Harris, Alan F. Morrison, Virendra V. S. Rana, James F. Roberts, Ashok K. Sinha, Simon Tam
  • Patent number: 5328872
    Abstract: Contamination of LPCVDBP TEOS films is reduced by preventing volatile compounds, resulting from reactions of the residue in the outlet of the furnace from reaching the deposition portion of the furnace where they would otherwise react with the deposition gases to produce chemically generated particles which contaminate the dielectric film.
    Type: Grant
    Filed: December 29, 1989
    Date of Patent: July 12, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Ajit S. Manocha, Virendra V. S. Rana, James F. Roberts, Ankineedu Velaga