Abstract: Apparatus, assemblies, and platforms employing modular power voltage regulator (VR) modules to provide power to memory modules. A power VR module includes VR circuitry integrated on or coupled to a substrate with wiring coupling the VR circuitry to connector elements in first and second connector means. An assembly further includes a pair of memory modules (e.g., DDR) that are coupled to a power VR module via mating connector means. The connector means may be coupled using a Compression Mount Technology (CMT) connector disposed between arrays of CMT contact pads on the power VR module and the memory modules, or may comprise BGAs, PGAs, and LGAs. The power VR module receives one or more input voltages via one or both memory module and provide various output voltages to each of the memory modules to power memory devices and other circuitry on those modules.

Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

Abstract: An example apparatus includes processor circuitry to execute instructions to determine memory usage data associated with a user profile, determine an address hashing policy based on the memory usage data, and determine power states of memory channels based on the address hashing policy.

Abstract: Systems, apparatuses, and methods may provide for optimizing the available memory in a power conscious compute platform. For example, a semiconductor apparatus includes logic to communicate with a system memory to divide a plurality of memory channels into functional channels and performance channels. The functional channels are in an active power state during a boot process and the performance channels are in an idle power state during the boot process. The semiconductor apparatus includes logic to track memory usage and bring the performance channels out of the idle power state and into the active power state in response to the tracked memory usage.

Abstract: Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.