Patents by Inventor Viresh P. Patel

Viresh P. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10304758
    Abstract: Techniques for forming a wafer level package device are disclosed. In one or more embodiments, the techniques include forming a wafer level lead frame on a carrier wafer and electrically connecting the wafer level lead frame to an active semiconductor wafer. The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion. The carrier wafer can be removed from the wafer level package device, and a number of connectors can be formed on the wafer level package device. The wafer level package device can be singulated to form chip packages, such as DFN or QFN packages.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 28, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC
    Inventors: Karthik Thambidurai, Ahmad Ashrafzadeh, Viresh P. Patel, Viren Khandekar
  • Publication number: 20170170159
    Abstract: A method for manufacturing a plurality of die pairs includes providing a first wafer including a plurality of spaced apart first dies arranged in a first array including a first, first die row and a second, first die row spaced apart by a first portion of a first row channel; providing a second wafer including a plurality of spaced apart second dies arranged in a second array including a first, second die row and a second, second die row spaced apart by a second portion of the first row channel; connecting the first wafer to the second wafer with a connector assembly to form a wafer pair such that the first dies and the second dies cooperate to form the plurality of die pairs; positioning a first support assembly between the first wafer and the second wafer to rigidly support the first wafer relative to the second wafer; and cutting along the first row channel with a blade to separate the plurality of die pairs from one another.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Srikanth Kulkarni, Viresh P. Patel
  • Publication number: 20170166442
    Abstract: A method of forming a plurality of sealed packages comprises providing a base including a base surface; providing a lid including a lid surface; positioning a plurality of spaced apart seal members along the base surface, the seal members being formed from a seal material including a fusible metal alloy; positioning the lid on the base with a plurality of spaced apart spacers positioned and extending between the base surface and the lid surface, the spacers maintaining the lid surface spaced apart from the seal members by a fluid gap, the spacers being made from a spacer material including a fusible metal alloy; creating a controlled environment around the base and the lid; and heating to melt the spacers and the seal material so that the seal members form a plurality of seal rings between the base surface and the lid surface.
    Type: Application
    Filed: December 11, 2015
    Publication date: June 15, 2017
    Inventors: Srikanth Kulkarni, Viresh P. Patel
  • Patent number: 9409765
    Abstract: The present invention relates to a method and apparatus for an isolating structure. Embodiments of the present invention provide a robust packaging process and a mechanical filter to reduce the mechanical shock from impact. The mechanical filter can be integrated within the package substrate as part of the packaging process, reducing the assembly complexity.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: August 9, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Hemant Desai, Viresh P. Patel
  • Patent number: 9250262
    Abstract: This invention relates generally to semiconductor manufacturing and packaging and more specifically to semiconductor manufacturing in MEMS (Microelectromechanical systems) inertial sensing products. Embodiments of the present invention provide a robust packaging process and a mechanical filter to reduce the mechanical shock from impact. The mechanical filter can be integrated within the package substrate as part of the packaging process, reducing the assembly complexity.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: February 2, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Hemant Desai, Viresh P. Patel