Abstract: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.

Abstract: A method, system and computer program product for reducing subexpressions in structural design representations containing AND and OR gates are disclosed. The method comprises receiving an initial design, in which the initial design represents an electronic circuit, containing an AND gate. A first simplification mode for the initial design from a set of applicable simplification modes is selected, wherein said simplification mode is an AND/OR simplification mode, and a simplification of the initial design according to the first simplification mode is performed to generate a reduced design. Whether a size of the reduced design is less than a size of the initial design is determined and, in response to determining that the size of the reduced design is less than the size of the initial design, the initial design is replaced with the reduced design.

Abstract: A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.

Abstract: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

Abstract: A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparamaterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.

Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.

Abstract: A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached.

Abstract: A method, system and computer program product for reducing XOR/XNOR subexpressions in structural design representations are disclosed. The method includes receiving an initial design, in which the initial design represents an electronic circuit containing an XOR gate. A first simplification mode for the initial design is selected from a set of applicable simplification modes, wherein the first simplification mode is an XOR/XNOR simplification mode, and a simplification of the initial design is performed according to the first simplification mode to generate a reduced design containing a reduced number of XOR gates. Whether a size of the reduced design is less than a size of the initial design is determined, and, in response to determining that the size of the reduced design is less than a the size of the initial design, the initial design is replaced with the reduced design.

Abstract: A method for performing verification is proposed. The method comprises receiving a design and building an intermediate binary decision diagram for the design containing one or more nodal binary decision diagrams. In response to a size of the intermediate binary decision diagram exceeding a size threshold, a node of the design is selected for case-splitting. A first case-splitting is performed upon the selected node of the design to generate a primary constraint for setting the selected node to a primary value. A first constraining is performed on one of the one or more nodal binary decision diagrams with the primary constraint to generate a primary final binary decision diagram, a first verification of the design is performed using the primary final binary decision diagram.

Abstract: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

Abstract: A method, system and computer program product for performing verification of an electronic design is disclosed. The method includes receiving a design, including a first target set, a primary input set, and a first register set comprising one or more registers. A binary decision diagram analysis of the design is generated. A recursive extraction of one or more next states of selected registers is generated using the binary decision diagram analysis of the first target set and the primary input set. The recursive extraction is decomposed to generate a second target set, and the second target set is verified.

Abstract: A method, system and computer program product for verifying that a design conforms to a desired property is disclosed. The method comprises receiving a design, a first initial state of the design, and a property for verification with respect to the design. The first initial state of the design is expanded to create a superset of the first initial state containing one or more states reachable from the first initial state of the design. A superset is synthesized to define a second initial state of the design. Application of the superset to the design is overapproximated through cutpoint insertion into the superset to obtain a modified superset, and the property is verified with reference to the modified superset.

Abstract: A method for performing verification is disclosed. The method includes selecting a first computer-design constraint for simplification and applying structural reparameterization to simplify the first computer-design constraint. In response to determining that the first computer-design constraint is not eliminated, the first computer-design constraint is set equal to a dead-end state of the constraint. A structural preimage of the first computer-design constraint is created, in response to determining that a combination of a target and the dead-end state of the first computer-design constraint is equal to a combination of the target and the structural preimage of the first computer-design constraint, the first computer-design constraint is set equal to the structural preimage.

Abstract: A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a reference latch logic cone, the reference constraint having a reference constraint logic cone and being associated with one of the reference latches; defining an implementation scan chain having implementation latches and an implementation constraint, each of the implementation latches having an implementation latch logic cone, the implementation constraint having an implementation constraint logic cone and being associated with one of the implementation latches; matching known corresponding scan points between the reference scan chain and the implementation scan chain; and determining scan chain functional correspondence between the reference latches and the implementation latches from the reference latch logic cones with any associated reference constraint logic cone and the implementation latch logic cones with an

Abstract: A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced (51) by pseudo inputs. The input signal values of the multiplier circuit are determined (54) automatically from a counterexample (53) delivered (52) by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined (55) with other known inputs to form a test case (56) file that can be used by a logic simulator to analyse the counterexample (52) on the unmodified hardware design including the multiplier.

Abstract: A method for performing trace equivalent identification by structural isomorphism detection, the method comprising: synthesizing a first netlist into a second netlist, the second netlist including two-input AND gates, inversions, inputs, constants, and registers; constructing a third netlist, the third netlist being a pseudo-canonical netlist that uses calls to algorithms for constructing a netlist for gate g1 and for constructing a netlist for gate g2, where g1 and g2 are gates; and performing an isomorphism check of gates g1 and g2.

Abstract: A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements. A cut of the initial design including one or more cut gates, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is constrained to force one or more constraint gates representing the one or more constraints to evaluate to a forced valuation, and one or more dead-end states of the constraints are identified. The inverse of the dead-end states is applied as don't cares to simplify the relation and the simplified relation is synthesized to form a first gate set. An abstracted design is from the first gate set and verification is performed on the abstracted design to generate verification results.

Abstract: A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g1 and a gate g2 in a netlist; mapping source gates of g1 with any permutation of source gates of g2 by using calls to an isomorphism detection algorithm; determining whether a permutation exists of pairings between the gates sourcing g1 and g2; resetting pairing of gates if the permutation exists; and eliminating pairwise-identical source gates of g1 and g2.

Abstract: A method for verifying a design through symbolic simulation is disclosed. The method comprises creating one or more binary decision diagram variables for one or more inputs in a design containing one or more state variables and building a binary decision diagram for a first node of one or more nodes of the design. A binary decision diagram for the initial state function of one or more state variables of the design is generated and the design is subsequently initialized. Binary decisions diagrams for one or more constraints are synthesized. A set of constraint values is accumulated over time by combining the binary decision diagrams for the one or more constraints with a set of previously generated binary decision diagrams for a set of constraints previously used in one or more previous time-steps. A binary decision diagram for the next state function of the one or more state variables in the design is constructed in the presence of the constraints.

Abstract: A system and method for implementing a verification system. Included is a first set of verification engines for attempting to solve a verification problem. At least one of the first set of verification engines divides the verification problem into a set of partitions and passes at least one of the set of partitions to a second set of verification engines. Each one of the set of partitions may be passed to a distinctly separate verification engine. A system framework is configured to communicate with an application program and further configured to instantiate at least one verification engine in a user-defined sequence. Included within at least one of the first set of verification engines is a means for communicating verification information to the second set of verification engines.