Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). Access commands are received from a host including disk read commands. When a high workload of disk access commands is detected, data of at least one disk read command is migrated to the NVSM.

Abstract: Disclosed herein is a data storage device comprising data storage media comprising a plurality of data sectors and control circuitry programmed to: receive a command from a host to cryptographically erase at least a portion of data stored on the data storage media; execute a cryptographic erase; receive a read command from the host to read a data sector in the data storage media; determine if the data sector has been cryptographically erased; and return configurable return data to the host in response to determining that the data sector has been cryptographically erased.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). When booting the hybrid drive in a first boot mode, the disk remains spun down, and when booting in a second boot mode, the disk is spun up. In one embodiment the hybrid drive receives a host command that configures the boot mode, and in another embodiment the hybrid drive determines the boot mode based on a state of the NVSM, such as an amount of free space or life remaining of the NVSM.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data tracks, and a non-volatile semiconductor memory (NVSM). An access command is received from a host, the access command identifying at least one target logical block address (LBA). When the target LBA is mapped to a target data track on the disk, the head is positioned over the target data track and an accumulated access time is updated for the target LBA. The accumulated access time is compared to a first threshold, and the target LBA is migrated to the NVSM in response to the comparison.

Abstract: A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). When a write command is received from a host that is mapped to the NVSM, the write command is serviced by writing data to the NVSM, and when a life remaining of the NVSM falls below a threshold, by also writing a copy of the data to the disk.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). A first execution time needed to execute commands in a NVSM command queue is estimated, and a second execution time needed to execute commands in a disk command queue is estimated. An access command is inserted into a selected one of the NVSM command queue and the disk command queue in response to the first and second execution times, and one of the first and second execution times is updated in response to an estimated execution time of the access command.

Abstract: Embodiments of the invention include systems and methods for reducing bus transfers for a storage device. In particular, these systems and methods reduce bus transfers by modifying an interface transfer protocol which designates the size of a multiple block read or write command is transmitted in a separate block transfer size command. Separate block transfer size commands can be omitted where the storage device maintains a record of a previously used block transfer size and reuses the size for subsequent multiple block read or write commands.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk, and a non-volatile semiconductor memory (NVSM). A write command is received from a host, the write command comprising data. First and second error correction code (ECC) symbols are generated over the data, wherein the second ECC symbols are different than the first ECC symbols. The data and first ECC symbols are written to the NVSM, and the second ECC symbols are written to the disk.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM). A read frequency of a first logical block address (LBA) is maintained, and when the read frequency of the first LBA exceeds a threshold and a corresponding PBA is assigned to a data sector of the disk, first data stored in the data sector is copied to a memory segment of the NVSM. When the read frequency of the first LBA exceeds a threshold and the PBA is assigned to a memory segment of the NVSM, first data stored in the memory segment is copied to a data sector of the disk. When a read command is received to read the first LBA, a decision is made to read the first data from one of the NVSM and the disk.

Abstract: A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently.

Abstract: A method of managing bad blocks in a RAID storage system. The system restores physical storage media and stripe redundancy by reassigning sectors and creating a bad block tracking structure. The bad block tracking structure consists of a volume map, a redundancy group table, and a bad block table that stores a bad block list. Redundancy is achieved through RAID 1 or RAID 10 mirroring rather than through the parity restoration required by conventional systems. The tracking structure returns media error status data to the originating host on volume read commands. The structure accepts volume write data from the originating host and then deletes the bad block tracking structure.

Abstract: A system for mapping between logical addresses and storage units of a plurality of storage volumes which comprise a storage system. For each volume, logical addresses are mapped to storage units using a volume mapping table. Each volume mapping table is comprised of a plurality of segments. Each segment need not be contiguously allocated to another segment of the same table. Thus, each volume mapping table can be independently expanded or reduced without affecting other volume mapping tables. A hash function, a hash table, a segment table, and a redundancy group descriptor table may also be used to help manage the segments of the volume mapping tables.

Abstract: An I/O controller having separate command and data paths, thereby eliminating the bandwidth used by the commands and thus increasing bandwidth available to the data buses. Additionally, the I/O controller uses multiple dedicated data paths, for example, dedicated distributed buses, and provides increased speed due to improved hardware integration. The I/O controller employs distributed processing methods that decouple the external microprocessor from much of the decision-making, thereby providing improved operating efficiency and thus more useable bandwidth at any given clock frequency. Accordingly, the I/O controller is capable of maximizing I/O operations (IOPS) on all I/O ports by functioning at the rate of I/O connections to hosts and storage elements without becoming a bottleneck.

Abstract: A method of predictive baseline volume profile creation for new volumes in a networked storage system and a system for dynamically reevaluating system performance and needs to create an optimized and efficient use of system resources by changing volume profiles as necessary. The system gathers statistical data and analyzes the information through algorithms to arrive at an optimal configuration for volume clusters. Clusters are then reallocated and reassigned to match the ideal system configuration for that point in time. The system continually reevaluates and readjusts its performance to meet throughput requirements specified in the quality of service agreement.

Abstract: A network storage system includes a network storage system controller/virtualizer which includes at least one transaction processor. When a host access request is received by the network storage system controller/virtualizer, the transaction processor calculates one or more cost functions. In one exemplary embodiment, a cost function associated with storage system volume load and a cost function associated with communication path load are calculated. The cost function result(s) are utilized by the storage system controller/virtualizer to form a request for servicing the host access request while balancing the load of the network storage system.

Abstract: A virtualizer module/element and a networked storage controller architecture with a virtualization layer that includes virtualizer modules. The virtualizer modules contain storage controller functionality as well as a cache subsystem. The virtualizer module processes primary data commands received from a host processor to determine if the cache subsystem of the virtualizer can service the data request or if it should be sent to a command mapper to retrieve the data from a downstream storage element. The cache subsystem of the virtualizer module thus enables reduced latency in the networked storage system as well as better management of storage devices and resources. The virtualizer module also facilitates predictive reads and read-ahead operations as well as coalesced write requests to a given storage device in order to increase system performance and storage device longevity.

Abstract: A storage element pending command queue prioritization system using multiple pending queues each assigned to a particular RAID command type. Pending commands from each of the queues are organized in such a way that lower priority commands are guaranteed a fixed amount of storage element bandwidth. Storage element throughput is optimized by limiting higher priority commands to a maximum service level and processing lower priority requests with the added storage element bandwidth, allowing lower priority requests to exceed their minimum service levels.

Abstract: A method of efficiently preventing data loss, specifically a RAID 5 write hole, in data storage system by storing valid parity information at the storage controller level during data write operations. The method employs the use of redundant data structures that hold metadata specific to outstanding writes and parity information. The method uses the redundant data structures to recreate the write commands and data when a system failure occurs before the writes have completed.

Abstract: A transaction processor pipeline architecture and associated apparatus for processing multiple queued transaction requests incorporates multiple processing elements working in parallel. Each processing element is configured to perform a specific function within the transaction processor system. Certain processing elements are assigned as function controllers, which are assigned to process specific transaction request subtask categories and may be augmented with dedicated hardware to accelerate certain subtask functions. Other processing elements are configured as list managers, which are optimized for managing data structure operations in memory. The processing elements are connected by a cross-point interconnect. The transaction processor system is configurable and scalable based on application needs.