Abstract: A normalizer that identifies the bits that are set in input data and generates output signals representing the positions of the set bits in the input data. The normalizer has a device arranged to receive an n-bit signal. Each of the bits of the n-bit signal are either set or clear. The normalizer operates iteratively, and during each iteration: determines an end most set bit; generates a signal representing position information for this end most set bit; and clears the end most set bit that was identified during the immediately previous iteration. The normalizer also includes a novel bit counter that provides a count of the number of bits set in the input data.

Abstract: The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vector from the sum of the operands and a precorrection factor. A second stage of the BCD adder circuit includes carry lookahead adder circuitry receiving as inputs the intermediate sum vector and the intermediate carry vector and producing a propagate vector and a final carry vector. The third stage of the BCD adder circuit conditionally modifies the propagate vector to form the BCD encoded sum according to bits of the intermediate carry vector and the final carry vector as inputs.