Abstract: An integrated electronic control circuit comprises a microcontroller connected to at least one volatile memory, at least one input/output port, a plurality of control devices, and an electronic non-volatile memory device comprising a non-volatile memory cell matrix linked to a control register, and a switch element connected between a voltage reference and the cell matrix to enable the program mode of the cell matrix under control by the microcontroller.

Abstract: The probability of soft-programming of the reference cells of a FLASH-EPROM memory may be excluded by having a decoupling transistor of a type of conductivity opposite to that of the cells functionally connected between the gate of each reference cell and the respective row line. Moreover the elimination of the electrical stresses to which the reference cells are subjected during the repeated programming cycles of the memory cells, increases the stability of the respective reference values of threshold and current level provided by the reference cells, thus increasing the reliability of the device.

Abstract: Each common source region of the cells of a row of a FLASH-EPROM matrix may be segmented and each segment is individually connected to a secondary source line patterned in a second level metal layer by a plurality of contacts between each common source region and patterned portions of a first level metal and through as many interconnection vias between the latter patterned portions of the first level of metal and the relative secondary source line patterned in the second metal layer. The secondary source lines are brought out of the matrix orthogonally to the bit lines and may be connected to a dedicated selection circuitry, thus permitting the erasing by groups or banks of cells of the FLASH-EPROM memory.