Patents by Inventor Virinder Singh

Virinder Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • I/O device layout during integrated circuit design
    Patent number: 6457157
    Abstract: A method for laying out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion. Also provided is a method for laying out pads for input/output (I/O) cells on an integrated circuit die in which size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: September 24, 2002
    Assignee: LSI Logic Corporation
    Inventors: Virinder Singh, Mike Liang
  • Method and apparatus for netlist filtering and cell placement
    Patent number: 6243849
    Abstract: Integrated circuit chip (IC) design and fabrication is a complex process requiring many stages including elaborate cell placement processes. The present invention provides a method and apparatus to facilitate the placement of cells on the surface of an integrated circuit device. Specifically, the invention involves placement of one type of cells (such as logic cells, I/O cells or scan cells) apart from other types of cells. The present invention facilitates the placement of such cells by first parsing the netlist to remove all cells other than the specific type of cells that are to be placed.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: June 5, 2001
    Assignee: LSI Logic Corporation
    Inventors: Virinder Singh, Mike Liang
  • Method for I/O device layout during integrated circuit design
    Patent number: 6057169
    Abstract: A method for laying out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion. Also provided is a method for laying out pads for input/output (I/O) cells on an integrated circuit die in which size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: May 2, 2000
    Assignee: LSI Logic Corporation
    Inventors: Virinder Singh, Mike Liang