Abstract: In a PECVD process, the plasma potential is controlled and maintained at a uniform level to confine the formed plasma to the gap area between the electrodes away from the influence of the walls of the discharge chamber. The plasma potential is controlled by operating the system at a high pressure, above about 12 Torr, and monitoring the operation by observing the DC bias on the upper or driven electrode until a positive potential, preferably greater than about 10V, is developed. At this point a symmetrical glow discharge and a controlled plasma exists between the driven electrode and the susceptor electrode, controllable by maintaining the pressure between about 14 and 20 Torr, to reduce plasma damage to the semiconductor body being coated which maximizes yield.

Abstract: A trench mask containing SiO.sub.2 is produced on a substrate (1) of single-crystal silicon. After deposition of a first Si.sub.3 N.sub.4 layer, first Si.sub.3 N.sub.4 spacers (31) are formed by anisotropic etching, and a first trench is etched to a first depth (t.sub.1). After selective removal of passivation layers arising in the first trench etching and after deposition of a second Si.sub.3 N.sub.4 layer, second Si.sub.3 N.sub.4 spacers (41) are formed by anisotropic etching. A second trench is etched to a second depth (t.sub.2), whereby the trench structure (5) is formed to a total depth (t.sub.1 and t.sub.2).

Abstract: In a process for global planarizing of surfaces for integrated semiconductor circuits a locally planarized insulation layer of silicon oxide with one thickness is initially applied on a structured layer to be planarized having another thickness. Photoresist structures are generated thereon as an auxiliary plane inversely to the structured plane lying below. A further well-adhering and planarizing auxiliary layer, preferably formed of spin-on glass, is applied. It must be selected as a function of a following anisotropic back-etching, in such a way that its etching rate is greater than that of the photoresist layer and nearly the same as that of the silicon oxide layer. The photoresist structures remaining after the back etching are removed. A further insulating layer formed of silicon oxide is applied up to the selected insulator thickness.