Patents by Inventor Vish SRINIVASAN

Vish SRINIVASAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941160
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 10, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Shao, Fan Zhang, Vish Srinivasan
  • Patent number: 9443761
    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposite within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: September 13, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wei Shao, Fan Zhang, Wuping Liu, Wei Lu, Vish Srinivasan, Juan Boon Tan
  • Publication number: 20160035623
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto. A contact opening exposing the metal silicide is formed to the semiconductor device. A conductive material is deposited within the contact opening to form a contact to the metal silicide while simultaneously forming a contact seam void within the contact. A self-aligned conductive material is deposited within the contact to form a conductive plug that at least partially fills the contact seam void, and a metallization layer is deposited overlying the contact.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 4, 2016
    Inventors: Wei Shao, Fan Zhang, Wuping Liu, Wei Lu, Vish Srinivasan, Juan Boon Tan
  • Publication number: 20150028490
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 29, 2015
    Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wei SHAO, Fan ZHANG, Vish SRINIVASAN