Abstract: A SIMD processor architecture (2) for processing a stream of data vectors is provided, the architecture comprising a processor array (4) comprising a plurality of processors (PE(0), . . . , (PE(N)), each processor ((PE(0), . . . PE(N)) being adapted to process a data element in each vector, the operation of the processor array (4) being controlled by a local clock signal having a first frequency; a control processor (16) adapted to control the operation of the SIMD processor architecture (2) and generate signals to synchronize the operation of the processor array (4) with the stream of data vectors, the operation of the control processor (16) being controlled by a local clock signal having a second frequency; and power management means (30) for adjusting the frequencies of the local clock signals in response to the synchronization signals generated by the control processor (16), thereby minimizing the power consumption of the SIMD processor architecture (2).

Abstract: A processor array has processor elements (2) and a memory (4), connected in parallel to the accessible in parallel by the processor elements (2). A separate serial module (30) provides additional functionality for example in the form of a look up table module (30). The serial module (3) processes lines of data input to the module (30) serially. Processing can continue in the processor elements (2) in parallel using suitable programming steps.

Abstract: A SIMD processor architecture (2) for processing a stream of data vectors is provided, the architecture comprising a processor array (4) comprising a plurality of processors (PE(0), . . . , (PE(N)), each processor ((PE(0), . . . PE(N)) being adapted to process a data element in each vector, the operation of the processor array (4) being controlled by a local clock signal having a first frequency; a control processor (16) adapted to control the operation of the SIMD processor architecture (2) and generate signals to synchronise the operation of the processor array (4) with the stream of data vectors, the operation of the control processor (16) being controlled by a local clock signal having a second frequency; and power management means (30) for adjusting the frequencies of the local clock signals in response to the synchronisation signals generated by the control processor (16), thereby minimising the power consumption of the SIMD processor architecture (2).

Abstract: A processor comprises a main controller (CTR11) and a plurality of processing units (1-9). Each processing unit (1-9) has a local controller (CTR1- CTR9) and at least one functional unit (FU1-FU9) controllable by the local controller (CTR1-CTR9). The local controller (CTR1-CTR9) of a processing unit (1-9) is coupled (15) to the main controller (CTR11). The processor further comprises an instruction set, having at least one instruction for increasing the activity of at least one processing unit (1-9). The main controller (CTR11) is arranged to process the at least one instruction for increasing the activity of at least one processing unit (1-9). One or more processing units (1-9) of the processor can be completely switched off, including the corresponding local controller (CTR1-CTR9), since the instructions for switching on a processing unit (1-9) are not processed by the corresponding local controller (CTR1-CTR9), but by the main controller (CTR11) itself.