Patents by Inventor Vishal Deep Ajmera

Vishal Deep Ajmera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240045801
    Abstract: Embodiments include methods to manage caches in a network device. In one embodiment, a method is performed by a network device and the method comprises determining a first cache of the network device is overloaded, where the first cache is within a cache hierarchy including a plurality of caches, each cache including a set of forwarding table entries for the network device to forward packets of traffic flows, and where one cache lower in the cache hierarchy is to be checked earlier in flow lookup than one higher in the cache hierarchy. The method further comprises upon determining that the first cache is overloaded, disabling the first cache from the flow lookup, where the flow lookup skips the first cache and is performed at a second cache higher in the cache hierarchy and disabling the first cache from forwarding table entry insertion when the forwarding table entry insertion is performed in one or more caches of the plurality of caches.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 8, 2024
    Inventors: Anju THOMAS, Nitin KATIYAR, Vishal Deep AJMERA, Venkatesan PRADEEP
  • Publication number: 20230262033
    Abstract: Various examples of the present disclosure relate to an apparatus, device, method, and computer program for a network element, to a corresponding network element and to a system.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 17, 2023
    Inventors: Bibhuti Bhusan TOSH, Peter MCCARTHY, Andriy GLUSTSOV, Chetan HIREMATH, John J. BROWNE, Greg THOMAS, Vishal DEEP AJMERA
  • Patent number: 11579678
    Abstract: A software switch and a method performed by the software switch are disclosed. The software switch receives, from a node deploying a virtual machine, a request for a virtual port to be polled by the virtual machine. The request includes a Central Processing Unit “CPU” identity identifying a CPU on which the virtual machine executes. The request includes an indication of a clock frequency at which the CPU is set to operate. The software switch determines a number of packets in a queue associated with the virtual port. The software switch adjusts the clock frequency of the CPU based on the number of packets in the queue. A corresponding computer program and a computer program carrier are also disclosed.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: February 14, 2023
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Nitin Katiyar, Vishal Deep Ajmera, Keshav Gupta, Anju Thomas
  • Patent number: 11360831
    Abstract: A method is implemented by a network device for orchestrating execution of a polling thread of a software-based switching program on a heterogeneous multicore processor. The method includes causing the polling thread to be executed on a first processing core in a first cluster of a plurality of clusters of processing cores, determining a value indicative of a number of active processing cycles used by the polling thread, determining whether the value is higher than a high threshold associated with the first processing core or lower than a low threshold associated with the first processing core, and if so causing the polling thread to be moved to a second processing core in a second cluster of the plurality of clusters, where the second processing core has a different processing capacity than the first processing core.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: June 14, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Vishal Deep Ajmera, Nitin Katiyar, Keshav Gupta, Anju Thomas
  • Publication number: 20220012108
    Abstract: A method is implemented by a network device for orchestrating execution of a polling thread of a software-based switching program on a heterogeneous multicore processor. The method includes causing the polling thread to be executed on a first processing core in a first cluster of a plurality of clusters of processing cores, determining a value indicative of a number of active processing cycles used by the polling thread, determining whether the value is higher than a high threshold associated with the first processing core or lower than a low threshold associated with the first processing core, and if so causing the polling thread to be moved to a second processing core in a second cluster of the plurality of clusters, where the second processing core has a different processing capacity than the first processing core.
    Type: Application
    Filed: December 24, 2018
    Publication date: January 13, 2022
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Vishal Deep Ajmera, Nitin Katiyar, Keshav Gupta, Anju Thomas
  • Publication number: 20210141435
    Abstract: A software switch and a method performed by the software switch are disclosed. The software switch receives, from a node deploying a virtual machine, a request for a virtual port to be polled by the virtual machine. The request includes a Central Processing Unit “CPU” identity identifying a CPU on which the virtual machine executes. The request includes an indication of a clock frequency at which the CPU is set to operate. The software switch determines a number of packets in a queue associated with the virtual port. The software switch adjusts the clock frequency of the CPU based on the number of packets in the queue. A corresponding computer program and a computer program carrier are also disclosed.
    Type: Application
    Filed: July 2, 2018
    Publication date: May 13, 2021
    Inventors: Nitin KATIYAR, Vishal Deep AJMERA, Keshav GUPTA, Anju THOMAS
  • Publication number: 20140298148
    Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Applicant: LSI Corporation
    Inventors: Santosh Narayanan, Benzeer Bava Arackal Pazhayakath, Vishal Deep Ajmera, Sandesh Kadirudyavara Ven Gowda
  • Patent number: 8782504
    Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: July 15, 2014
    Assignee: LSI Corporation
    Inventors: Santosh Narayanan, Benzeer Bava Arackal Pazhayakath, Vishal Deep Ajmera, Sandesh Kadirudyavara Ven Gowda
  • Publication number: 20130275843
    Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.
    Type: Application
    Filed: April 11, 2012
    Publication date: October 17, 2013
    Applicant: LSI Corporation
    Inventors: Santosh Narayanan, Benzeer Bava Arackal Pazhayakath, Vishal Deep Ajmera, Sandesh Kadirudyavara Ven Gowda