Patents by Inventor Vishal Khandelwal
Vishal Khandelwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240086394Abstract: The disclosure deals with a system and method for improved representation and retrieval of recipes or workflows. Recipes or workflows such as for preparing food or assembling furniture or performing other complex activities exist as textual or image documents, which makes it difficult for machines to read, reason, and handle ambiguity. The present disclosure provides a Rich Recipe Representation (“R3”), which is enhanced with additional knowledge such as outcomes like allergen information, possible failures, and solutions for each atomic step (such as a cooking step). The disclosed R3 is used in a web-based decision support system that helps users perform constrained queries using multiple modalities while also monitoring execution of an agent cooking or otherwise acting based on it.Type: ApplicationFiled: August 25, 2023Publication date: March 14, 2024Inventors: BIPLAV SRIVASTAVA, VISHAL PALLAGANI, REVATHY CHANDRASEKARAN VENKA, VEDANT KHANDELWAL, KAUSIK LAKKARAJU
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Patent number: 11836641Abstract: When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML) model to predict, based on features of partial circuit designs at early stages of the design flow, whether the full circuit is likely to meet the constraints. Additionally, the disclosed approaches allow for the ranking of various circuit designs or design implementations to determine best candidates to proceed with the full design.Type: GrantFiled: March 15, 2021Date of Patent: December 5, 2023Assignee: SYNOPSYS, INC.Inventors: Ravi Mamidi, Siddhartha Nath, Wei-Ting Chan, Vishal Khandelwal
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Patent number: 11741282Abstract: Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.Type: GrantFiled: January 19, 2022Date of Patent: August 29, 2023Assignee: Synopsys, Inc.Inventors: Siddhartha Nath, Vishal Khandelwal, Yi-Chen Lu, Praveen Ghanta
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Patent number: 11636388Abstract: A machine learning (ML) system is trained to predict the number of design rules violations of a circuit design that includes a multitude of Gcells. To achieve this, a netlist associated with the circuit design is placed by a place and route tool. A first list of features associated with the placed netlist is delivered to the ML system. A global route of the circuit design is performed by a global router. Next, a second list of features is delivered from the global router to the ML system. Thereafter, a detailed route of the circuit design is performed by a detailed router. A label associated with each Gcell in the circuit design is delivered to the ML system from the detailed route. The ML system is trained using the first and second list of features and the labels.Type: GrantFiled: February 4, 2020Date of Patent: April 25, 2023Assignee: Synopsys, Inc.Inventors: Wei-Ting Chan, Siddhartha Nath, Vishal Khandelwal
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Publication number: 20220229960Abstract: Systems and methods for adjusting a digital circuit design are described. For example, the method may include selecting a first path in the digital circuit design. The first path includes a plurality of gates. The method also includes generating a k-hop neighborhood graph of the first path, encoding the k-hop neighborhood graph into a state vector, and applying a machine learning model to the state vector to determine an adjustment to be made on a first gate of the plurality of gates. The method further includes changing the first gate based on the adjustment.Type: ApplicationFiled: January 19, 2022Publication date: July 21, 2022Inventors: Siddhartha NATH, Vishal KHANDELWAL, Yi-Chen LU, Praveen GHANTA
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Patent number: 11256845Abstract: Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.Type: GrantFiled: September 9, 2020Date of Patent: February 22, 2022Assignee: Synopsys, Inc.Inventors: Siddhartha Nath, Vishal Khandelwal, Sudipto Kundu, Ravi Mamidi
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Publication number: 20210287120Abstract: When designing circuits to meet certain constraint requirements, it is challenging to determine whether a given circuit design will meet the constraints. A designer at an early stage of the circuit design (e.g., synthesis or placement) may have limited information to rely on in order to determine whether the eventual circuit, or some design variation thereof, will satisfy those constraints without fully designing the circuit. The approaches described herein use a machine learning (ML) model to predict, based on features of partial circuit designs at early stages of the design flow, whether the full circuit is likely to meet the constraints. Additionally, the disclosed approaches allow for the ranking of various circuit designs or design implementations to determine best candidates to proceed with the full design.Type: ApplicationFiled: March 15, 2021Publication date: September 16, 2021Applicant: Synopsys, Inc.Inventors: Ravi MAMIDI, Siddhartha NATH, Wei-Ting CHAN, Vishal KHANDELWAL
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Publication number: 20210073456Abstract: Training data is collected for each training integrated circuit (IC) design of a set of training IC designs by: extracting a first set of IC design features in a first stage of an IC design flow, and extracting a first set of IC design labels in a second stage of the IC design flow, where the first stage of the IC design flow occurs earlier than the second stage of the IC design flow in the IC design flow. Next, a machine learning model is trained based on the training data.Type: ApplicationFiled: September 9, 2020Publication date: March 11, 2021Applicant: Synopsys, Inc.Inventors: Siddhartha Nath, Vishal Khandelwal, Sudipto Kundu, Ravi Mamidi
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Patent number: 9245075Abstract: Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.Type: GrantFiled: December 2, 2014Date of Patent: January 26, 2016Assignee: SYNOPSYS, INC.Inventors: Yiu-Chung Mang, Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee
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Publication number: 20150089462Abstract: Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.Type: ApplicationFiled: December 2, 2014Publication date: March 26, 2015Inventors: Yiu-Chung Mang, Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee
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Patent number: 8924901Abstract: Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.Type: GrantFiled: October 31, 2013Date of Patent: December 30, 2014Assignee: Synopsys, Inc.Inventors: Yiu-Chung Mang, Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee
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Publication number: 20140237437Abstract: Systems and techniques are described for performing circuit synthesis. Some embodiments create a lookup table based on information contained in a cell library. The lookup table is then used during circuit synthesis. Specifically, some embodiments optimize cells in a reverse-levelized cell ordering. For a given cell, a table lookup is performed to obtain a set of optimal cell configurations, and the cell is replaced with a cell configuration selected from the set of optimal cell configurations. Some embodiments concurrently optimize cells for timing, area, and power leakage based on the timing criticality of the cells.Type: ApplicationFiled: October 31, 2013Publication date: August 21, 2014Applicant: Synopsys, Inc.Inventors: Yiu-Chung Mang, Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee
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Patent number: 7853915Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.Type: GrantFiled: June 24, 2008Date of Patent: December 14, 2010Assignee: Synopsys, Inc.Inventors: Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, Jing C. Lin, Mahesh A. Iyer
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Publication number: 20090319977Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.Type: ApplicationFiled: June 24, 2008Publication date: December 24, 2009Applicant: Synopsys, Inc.Inventors: Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, Jing C. Lin, Mahesh A. Iyer