Abstract: A substrate has an active area including first and second doped regions separated by portions of the substrate. Gates are located over the active area, each gate formed extending over a portion of the substrate separating adjacent first and second doped regions. A length of the doped regions is greater than other devices within the substrate that have a same gate oxide thickness. A first metallization layer has first electrical connectors between each of the first doped regions and a gate immediately adjacent thereto, and second electrical connectors connected to each of the second doped regions. A second metallization layer has a first electrical connector connected to each first electrical connector of the first metallization layer, and a second electrical connector connected to each second electrical connector of the first metallization layer, with the second electrical connector of the second metallization layer not overlapping the gates.

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

Abstract: A substrate has an active area including first and second doped regions separated by portions of the substrate. Gates are located over the active area, each gate formed extending over a portion of the substrate separating adjacent first and second doped regions. A length of the doped regions is greater than other devices within the substrate that have a same gate oxide thickness. A first metallization layer has first electrical connectors between each of the first doped regions and a gate immediately adjacent thereto, and second electrical connectors connected to each of the second doped regions. A second metallization layer has a first electrical connector connected to each first electrical connector of the first metallization layer, and a second electrical connector connected to each second electrical connector of the first metallization layer, with the second electrical connector of the second metallization layer not overlapping the gates.

Abstract: A circuit includes a logic circuit and a driver. The driver includes a first NMOS having a gate coupled to the logic circuit and source coupled to a reference voltage, a PAD coupled to a drain of the first NMOS, and a driver protection circuit. The driver protection circuit includes a second NMOS having a drain coupled to the PAD through a capacitor, source coupled to the reference voltage, and gate coupled to a supply voltage, and a resistor coupled between the drain of the second NMOS and the bulk of the first NMOS. The supply voltage transitions low when an electrostatic discharge (ESD) event raises potential at the PAD with respect to either reference voltage or supply voltage such that the second NMOS turns off, resulting in isolation of the bulk of first NMOS from the reference voltage and coupling of the bulk to the PAD using the capacitor.

Abstract: A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

Abstract: In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.

Abstract: A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area.