Abstract: A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics.

Abstract: A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics.

Abstract: A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics.

Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.

Abstract: A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics.

Abstract: A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics. At least one thread is allocated to one of the primary power regions, based on thread characteristics. At least one page is allocated to one of the primary power regions, based on page characteristics.

Abstract: A computing system having a plurality of processing units configured to perform work by having threads assigned to the processing units. A thread scheduler is coupled to the plurality of processors and configured to schedule threads to the processing units. A power manager is coupled to the thread scheduler and controls performance states or idle states of the processing units. The thread scheduler maintains information about current performance state or idle state per processing unit. The information includes a multi-level description of the processing units in the computing system. The multi-level description includes three or more different entry values of different levels for performance state or idle state for processing units. The power manager provides the multi-level description of the processing units to the thread scheduler, which is configured to schedule threads to the processing units based on the multi-level description.

Abstract: A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics. At least one thread is allocated to one of the primary power regions, based on thread characteristics. At least one page is allocated to one of the primary power regions, based on page characteristics.

Abstract: A computing system having a plurality of processing units configured to perform work by having threads assigned to the processing units. A thread scheduler is coupled to the plurality of processors and configured to schedule threads to the processing units. A power manager is coupled to the thread scheduler and controls performance states or idle states of the processing units. The thread scheduler maintains information about current performance state or idle state per processing unit. The information includes a multi-level description of the processing units in the computing system. The multi-level description includes three or more different entry values of different levels for performance state or idle state for processing units. The power manager provides the multi-level description of the processing units to the thread scheduler, which is configured to schedule threads to the processing units based on the multi-level description.

Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.

Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.

Abstract: A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.

Abstract: Techniques for implementing processor state-based thread scheduling are described that improve processor performance or energy efficiency of a computing device. In one or more embodiments, a power configuration state of a processor is ascertained. The processor or another processor is selected to execute a thread based on the power configuration state of the processor. In other embodiments, power configuration states of processor cores are ascertained. Power configuration state criteria for the processor cores are defined based on the respective power configuration states. One of the processor cores is then selected based on the power configuration state criteria to execute a thread.

Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.

Abstract: A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.