Patents by Inventor Vishal Tripathi

Vishal Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956808
    Abstract: This disclosure provides systems, methods, and apparatus, including computer programs encoded on computer-readable media, for managing scheduling requests (SRs) in a user equipment (UE) that supports a split data radio bearer (DRB). In some aspects, the UE may trigger a first SR for a first communication link and a second SR for a second communication link in response to determining that a first amount of data in the UE data buffer is greater than a first threshold. The UE may transmit the first SR to a first base station (BS) via the first communication link. Prior to transmission of the second SR, the UE may determine whether a second amount of data in the UE data buffer is less than a second threshold. The UE may cancel the second SR in response to the second amount of data in the UE data buffer being less than the second threshold.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: April 9, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Akshay Kumar, Arnaud Meylan, Leena Zacharias, Michel Chauvin, Vishal Dalmiya, Ambarish Tripathi, Shailesh Maheshwari, Sathyanarayanan Raghunathan, Baojun Lu
  • Publication number: 20240111932
    Abstract: Multiple classifier models are applied to features of a circuit design after processing the design through a first phase of an implementation flow. Each classifier model is associated with one of multiple directives, the directives are associated with a second phase of the implementation flow, and each classifier model returns a value indicative of likelihood of improving a quality metric. Regressor models of each set of a plurality of sets of regressor models are applied to the features. Each directive is associated with one of the sets of regressor models, and a combined score from each set of regressor models indicates a likelihood of satisfying a constraint. The directives are ranked based on the values indicated by the classifier models and scores from the sets of regressor models, and the circuit design is processed n the second phase of the implementation flow by the design tool using the directive having the highest rank.
    Type: Application
    Filed: October 3, 2022
    Publication date: April 4, 2024
    Applicant: Xilinx, Inc.
    Inventors: Satish Bachina, Karthic P, Vishal Tripathi, Srinivasan Dasasathyan