Patents by Inventor Vishal Trivedi
Vishal Trivedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11915983Abstract: A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate.Type: GrantFiled: January 25, 2023Date of Patent: February 27, 2024Assignee: APPLIED NOVEL DEVICES, INC.Inventors: Leo Mathew, Rajesh Rao, Daniel Fine, Vishal Trivedi
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Publication number: 20230170263Abstract: A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate.Type: ApplicationFiled: January 25, 2023Publication date: June 1, 2023Inventors: LEO MATHEW, RAJESH RAO, DANIEL FINE, VISHAL TRIVEDI
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Patent number: 11610819Abstract: A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate.Type: GrantFiled: July 16, 2020Date of Patent: March 21, 2023Assignee: APPLIED NOVEL DEVICES, INC.Inventors: Leo Mathew, Rajesh Rao, Daniel Fine, Vishal Trivedi
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Publication number: 20220020645Abstract: A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate.Type: ApplicationFiled: July 16, 2020Publication date: January 20, 2022Applicant: APPLIED NOVEL DEVICES, INC.Inventors: LEO MATHEW, RAJESH RAO, DANIEL FINE, VISHAL TRIVEDI
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Patent number: 10269943Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.Type: GrantFiled: August 14, 2017Date of Patent: April 23, 2019Assignee: NXP USA, INC.Inventors: Jay Paul John, Vishal Trivedi, James Albert Kirchgessner
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Publication number: 20180102421Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.Type: ApplicationFiled: August 14, 2017Publication date: April 12, 2018Inventors: JAY PAUL JOHN, VISHAL TRIVEDI, JAMES ALBERT KIRCHGESSNER
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Patent number: 9786770Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.Type: GrantFiled: October 6, 2016Date of Patent: October 10, 2017Assignee: NXP USA, INC.Inventors: Jay Paul John, Vishal Trivedi, James Albert Kirchgessner
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Patent number: 9665732Abstract: A method and system for secure download includes generating a path to a location where a downloadable object is temporarily stored. The method can include receiving a request for a downloadable object, generating one or more unique identifiers, creating a path to the requested object using the unique identifiers, storing a copy of the requested object in a temporary location indicated by the path, and returning the generated path to the requestor. The method can further include receiving a path to a downloadable object and, responsive to a determination that the path is valid, returning the downloadable object. A generated path can be rendered obsolete and its corresponding file removed from the temporary location after a predefined time interval has elapsed. A database of the generated paths and associated files may be periodically checked, and those paths and files that have been stored in the database beyond a pre-definable expiry time can be removed.Type: GrantFiled: July 2, 2014Date of Patent: May 30, 2017Assignee: SAP SEInventors: Aswin Kumar Jayaraman, Vishal Trivedi, Raghavendra Rao M G
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Publication number: 20160004850Abstract: A method and system for secure download includes generating a path to a location where a downloadable object is temporarily stored. The method can include receiving a request for a downloadable object, generating one or more unique identifiers, creating a path to the requested object using the unique identifiers, storing a copy of the requested object in a temporary location indicated by the path, and returning the generated path to the requestor. The method can further include receiving a path to a downloadable object and, responsive to a determination that the path is valid, returning the downloadable object. A generated path can be rendered obsolete and its corresponding file removed from the temporary location after a predefined time interval has elapsed. A database of the generated paths and associated files may be periodically checked, and those paths and files that have been stored in the database beyond a pre-definable expiry time can be removed.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Aswin Kumar Jayaraman, Vishal Trivedi, Raghavendra Rao M G
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Patent number: 8074215Abstract: Operation of a computer system is governed by an executable application and settings set forth in an XML document to which the application refers during execution. When an application is published for installation, it includes the application and a base XML document. Portions of the base XML document are marked as editable during installation. During installation, an installation manager review the base XML document, identifies editable portions therein and reads installation settings data therefor. The installation manager may generate a modified XML document representing the settings of the base XML document and any modified settings obtained for installation. Modified settings data may be obtained from an operator, from a computer system on which installation occurs or from a dataset representing settings data obtained in prior installations.Type: GrantFiled: April 14, 2006Date of Patent: December 6, 2011Assignee: SAP AGInventors: Dror Cohen, David Rachamim, Yiftach Nun, Ronen Rubinfeld, Vishal Trivedi
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Patent number: 7774298Abstract: The present invention provides a method and system for the automatic extraction of data from a transaction system to an analytics system, which is capable of handling large volumes of application data.Type: GrantFiled: June 30, 2004Date of Patent: August 10, 2010Assignee: SAP AGInventors: Vishal Trivedi, Venkiteswaran B. Vadakkencherry
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Publication number: 20070245340Abstract: Operation of a computer system is governed by an executable application and settings set forth in an XML document to which the application refers during execution. When an application is published for installation, it includes the application and a base XML document. Portions of the base XML document are marked as editable during installation. During installation, an installation manager review the base XML document, identifies editable portions therein and reads installation settings data therefor. The installation manager may generate a modified XML document representing the settings of the base XML document and any modified settings obtained for installation. Modified settings data may be obtained from an operator, from a computer system on which installation occurs or from a dataset representing settings data obtained in prior installations.Type: ApplicationFiled: April 14, 2006Publication date: October 18, 2007Inventors: Dror Cohen, David Rachamim, Yiftach Nun, Ronen Rubinfeld, Vishal Trivedi
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Publication number: 20060004833Abstract: The present invention provides a method and system for the automatic extraction of data from a transaction system to an analytics system, which is capable of handling large volumes of application data.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Inventors: Vishal Trivedi, Venkiteswaran Vadakkencherry