Abstract: Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically, blockers can be formed in the 0 degree phase shifters. In this configuration, the intensity associated with the 0 degree phase shifters approximates the intensity associated with the corresponding 180 degree phase shifters. Intensity balancing using blockers retains image contrast, thereby ensuring printed feature quality.

Abstract: Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically, blockers can be formed in the 0 degree phase shifters. In this configuration, the intensity associated with the 0 degree phase shifters approximates the intensity associated with the corresponding 180 degree phase shifters. Intensity balancing using blockers retains image contrast, thereby ensuring printed feature quality.

Abstract: Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically, blockers can be formed in the 0 degree phase shifters. In this configuration, the intensity associated with the 0 degree phase shifters approximates the intensity associated with the corresponding 180 degree phase shifters. Intensity balancing using blockers retains image contrast, thereby ensuring printed feature quality.

Abstract: A method of correction for design data includes the steps of sequentially applying a plurality of corrections to a plurality of features based on a plurality of feature tolerances to design data in a predetermined order, and providing corrected design data.

Abstract: Using phase shifting on a mask can advantageously improve printed feature resolution on a wafer, thereby allowing greater feature density on an integrated circuit. Phase shifting can create an intensity imbalance between 0 degree and 180 degree phase shifters on the mask. An improved method of designing an alternating PSM to minimize this intensity imbalance is provided. Sub-resolution features, called “blockers”, can be incorporated in the alternating PSM design. Specifically, blockers can be formed in the 0 degree phase shifters. In this configuration, the intensity associated with the 0 degree phase shifters approximates the intensity associated with the corresponding 180 degree phase shifters. Intensity balancing using blockers retains image contrast, thereby ensuring printed feature quality.

Abstract: An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.

Abstract: An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.