Patents by Inventor Vishnu Kumar
Vishnu Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11334389Abstract: The latency corresponding to a latency-sensitive event-based processor is evaluated to determine whether the latency-sensitive event-based processor (EBP) should be prioritized. If so, constraints on the number of events that the latency-sensitive EBP can process are relaxed and the frequency with which the latency-sensitive EBP can process events is increased. At a next latency evaluation, if the latency-sensitive EBP no longer meets criteria for prioritization, the constraint on the number of events is returned to a nominal level, as is the frequency with which the latency-sensitive EBP can process events.Type: GrantFiled: October 30, 2019Date of Patent: May 17, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Priyadarshi Ghosh, Anand Patil, Vishnu Kumar, Aparajita
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Publication number: 20210124621Abstract: The latency corresponding to a latency-sensitive event-based processor is evaluated to determine whether the latency-sensitive event-based processor (EBP) should be prioritized. If so, constraints on the number of events that the latency-sensitive EBP can process are relaxed and the frequency with which the latency-sensitive EBP can process events is increased. At a next latency evaluation, if the latency-sensitive EBP no longer meets criteria for prioritization, the constraint on the number of events is returned to a nominal level, as is the frequency with which the latency-sensitive EBP can process events.Type: ApplicationFiled: October 30, 2019Publication date: April 29, 2021Inventors: Priyadarshi GHOSH, Anand PATIL, Vishnu KUMAR, Aparajita
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Patent number: 10963610Abstract: The present embodiments are generally directed to analyzing clock jitter. Jitter affects the clock delay of the circuit and the time the clock is available at sync points, so it is important to calculate its impact correctly to take appropriate margin during timing analysis. Jitter could be due to various reasons—one of them is due to IR Impact on the Clock Tree. IR drop variations between the two consecutive cycles can effectively reduce the available clock period for data to be correctly captured.Type: GrantFiled: May 22, 2020Date of Patent: March 30, 2021Assignee: Cadence Design Systems, Inc.Inventors: Igor Keller, Vishnu Kumar
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Patent number: 10897533Abstract: A calendar application on a communication device generates a user interface that allows a user to interact with a representation of a calendar event. The calendar application detects a user configuration input indicative of how to control the communication device, in responding to a real-time communication event, during the calendar event. When the real-time communication event is detected during the calendar event, the calendar application controls the communication device based upon the configuration input.Type: GrantFiled: October 22, 2019Date of Patent: January 19, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Priyadarshi Ghosh, Nikhil Narendraji Daf, Arun Dixit, Vishnu Kumar, Anand Patil
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Patent number: 10031986Abstract: The present disclosure relates to a system and method for performing Path-Based Analysis (PBA) of an electronic circuit design. Embodiments may include receiving a command to create a spice deck of a timing path associated with the electronic circuit design. In response to receiving the command, embodiments may further include initiating PBA for the timing path and identifying one or more stages within the timing path. Embodiments may also include performing a delay calculation for each of the one or more stages and generating a stage spice deck for each of the one or more stages based upon, at least in part, information from the delay calculation, wherein the stage spice deck encapsulates all elements of the stage. Embodiments may further include connecting the stage spice deck for each of the one or more stages in series to form a complete path spice deck.Type: GrantFiled: March 31, 2016Date of Patent: July 24, 2018Assignee: Cadence Design Systems, Inc.Inventors: Vishnu Kumar, Manuj Verma
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Patent number: 9589096Abstract: Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.Type: GrantFiled: May 19, 2015Date of Patent: March 7, 2017Assignee: Cadence Design Systems, Inc.Inventors: Umesh Gupta, Vishnu Kumar, Manish Bansal, Naresh Kumar, Manuj Verma, Prashant Sethia
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Patent number: 7986114Abstract: A motor driver comprises a first power supply, a second power supply, a multiplexer, and an output power module. The first power supply provides a first power signal after a first period. The second power supply provides a second power signal after a second period, where the second period is longer than the first period. The multiplexer initially selects the first power signal and then selects the second power signal. An output power module controls a motor and receives power from an output of the multiplexer.Type: GrantFiled: June 30, 2010Date of Patent: July 26, 2011Assignee: Marvell International Ltd.Inventors: Ying Tian Li, Vishnu Kumar
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Patent number: 7839102Abstract: A circuit system and process utilizes back electromotive force (BEMF) voltage to assist in safe power down of devices, such as the read/write head in from low factor disk drives or similar devices. The BEMF voltage from a motor device, such as a spindle motor utilized in a circuit using negative voltage to drive some switches, such as positive channel metal oxide semiconductor (“PMOS”) driver transistors, to reduce and/or effectively minimize the on-resistance of the switches while delivering the current from BEMF voltage of the motor to another device, such as a motor that retracts controls a read/write head.Type: GrantFiled: June 29, 2009Date of Patent: November 23, 2010Assignee: Marvell International LtdInventors: Sakti Pada Rana, Kuong Hoo, legal representative, Vishnu Kumar, Siew Yong Chui
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Patent number: 7750584Abstract: A motor driver comprises a first power supply, a second power supply, a multiplexer, and an output power module. The first power supply provides a first power signal after a first period. The second power supply provides a second power signal after a second period, where the second period is longer than the first period. The multiplexer initially selects the first power signal and then selects the second power signal. An output power module controls a motor and receives power from an output of the multiplexer.Type: GrantFiled: August 16, 2007Date of Patent: July 6, 2010Assignee: Marvell International Ltd.Inventors: Ying Tian Li, Vishnu Kumar
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Patent number: 7560883Abstract: A circuit system and process utilizes back electromotive force (BEMF) voltage to assist in safe power down of devices, such as the read/write head in from low factor disk drives or similar devices. The BEMF voltage from a motor device, such as a spindle motor utilized in a circuit using negative voltage to drive some switches, such as positive channel metal oxide semiconductor (“PMOS”) driver transistors, to reduce and/or effectively minimize the on-resistance of the switches while delivering the current from BEMF voltage of the motor to another device, such as a motor that retracts controls a read/write head.Type: GrantFiled: February 5, 2008Date of Patent: July 14, 2009Assignee: Marvell International, Ltd.Inventors: Kuong Hoo, legal representative, Vishnu Kumar, Siew Yong Chui, Sakti Pada Rana
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Patent number: 7327106Abstract: A circuit system and process utilizes back electromotive force (BEMF) voltage to assist in safe power down of devices, such as the read/write head in from low factor disk drives or similar devices. The BEMF voltage from a motor device, such as a spindle motor utilized in a circuit using negative voltage to drive some switches, such as positive channel metal oxide semiconductor (“PMOS”) driver transistors, to reduce and/or effectively minimize the on-resistance of the switches while delivering the current from BEMF voltage of the motor to another device, such as a motor that retracts controls a read/write head.Type: GrantFiled: May 1, 2007Date of Patent: February 5, 2008Assignee: Marvell International, LtdInventors: Kuong Hoo, legal representative, Vishnu Kumar, Siew Yong Chui, Sakti Pada Rana, deceased
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Patent number: 7211973Abstract: A circuit system and process utilizes back electromotive force (BEMF) voltage to assist in safe power down of devices, such as the read/write head in from low factor disk drives or similar devices. The BEMF voltage from a motor device, such as a spindle motor utilized in a circuit using negative voltage to drive some switches, such as positive channel metal oxide semiconductor (“PMOS”) driver transistors, to reduce and/or effectively minimize the on-resistance of the switches while delivering the current from BEMF voltage of the motor to another device, such as a motor that retracts controls a read/write head.Type: GrantFiled: July 13, 2005Date of Patent: May 1, 2007Assignee: Marvell Asia PTE, Ltd.Inventors: Kuong Hoo, legal representative, Vishnu Kumar, Siew Yong Chui, Sakti Pada Rana, deceased
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Publication number: 20060093320Abstract: A Personal Video Recorder (PVR) generates an object index table in real-time that can be updated while streaming media is being encoded and stored in memory. This allows more dynamic video trick mode operations such as fast forward, reverse and skip. The PVR also provides automatic data rate control that prevents video frames from being dropped thus preventing jitter in the output media.Type: ApplicationFiled: October 17, 2005Publication date: May 4, 2006Inventors: Bryan Hallberg, Kim Wells, Vishnu Kumar
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Publication number: 20050149969Abstract: A method for displaying content on a video display comprising the steps of coupling the video display with an external storage device having content files stored thereon. The content files from the external storage device are then grouped into one or more groups of content files by file type. Each of the groups are associated with a selectable icon, and the grouped content files of a particular type are displayed on the video display responsive to selection of the associated icon.Type: ApplicationFiled: October 22, 2004Publication date: July 7, 2005Inventors: Vishnu Kumar, Mark Hanley
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Publication number: 20050149990Abstract: Java Applets are packaged in a JAR file, including accompanying classes and resources as well as one addition file—a descriptor file. This last file can be read from the JAR file, and scanned to extract an icon to represent the applet on a menu, the applet's name in market applicable languages, applet size and position, and the applets main class name. No further processing need be done to present this applet to the user for selection. The entire applet need not be loaded into memory until the user requests it by using a remote control to select one of the applets represented on the display by a labeled icon. Once the user has selected the application, the applet can be sized and launched without further scanning.Type: ApplicationFiled: October 29, 2004Publication date: July 7, 2005Inventors: Jon Fairhurst, Bryan Hallberg, Mark Hanley, Vishnu Kumar, Henry Fang, Jeffrey Sampsell