Abstract: An Advanced Encryption Standard (AES) device and a computer-implemented method of performing an AES operation may be provided, the AES device comprising a state array of components comprising a first plurality of controllable data processing components, the first plurality of controllable data processing components including two or more controllable data processing state members that each include an additional input control and an additional input port; a key array of components comprising a second plurality of controllable data processing components; a control block module coupled to the state array of components and the key array of components, the control block module arranged to transmit one or more control signals to the state array of components and the key array of components; wherein the two or more controllable data processing state members are disposed at predetermined positions within the state array of components; and further wherein the control block module is arranged to instruct performance of

Abstract: There is provided a neural network processor system including: a neural processing unit including a plurality of neural processing cores; a router network including a plurality of routers communicatively coupled to the plurality of neural processing cores, respectively; and a host processing unit communicatively coupled to the neural processing unit based on the router network and configured to coordinate the neural processing unit for performing neural network computations.

Abstract: There is provided a neurosynaptic processing core with spike time dependent plasticity (STDP) learning for a spiking neural network, including: a spiking neuron block including a pre-synaptic block and a post-synaptic block; a synapse block communicatively coupled to the spiking neuron block; a STDP learning block communicatively coupled to the spiking neuron block and the synapse block, the STDP learning block including a pre-synaptic event accumulator including a pre-synaptic spike event memory block and a pre-synaptic spike parameter modifier; a post-synaptic event accumulator including a post-synaptic spike event memory block and a post-synaptic spike parameter modifier, a weight change accumulator, and a weight change parameter modifier; a learning error modulator; and a synaptic weight modifier configured to modify a synaptic weight parameter based on a weight change parameter and a learning error corresponding to the synaptic weight parameter.

Abstract: There is provided a neural network processor system including: a plurality of neural processing units, including a first neural processing unit and a second neural processing unit, whereby each neural processing unit comprises an array of neural processing core blocks, each neural processing core block comprising a neural processing core; and at least one central processing unit communicatively coupled to the plurality of neural processing units and configured to coordinate the plurality of neural processing units for performing neural network computations. In particular, the first and second neural processing units have a different structural configuration to each other. There is also provided a corresponding method of operating and a corresponding method of forming the neural network processor system.