Patents by Inventor Vishnu Prasad
Vishnu Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11798037Abstract: Advertising audience segment creators, including methods, systems, and apparatuses for automated creation of audience segments in advertising platforms are disclosed herein. Data may be received at a processor of an application server from a remote device. The data may be related to a user of the remote device. An audience member may be retrieved from an audience database. The audience member may correspond to an external identifier of the user. The audience database may be stored on an electronic storage device. The audience member may be assigned to an event. The assigning of the audience member to the event may be based on the data. Assigning the audience member to the event may be based on a refresh interval. The refresh interval may be of an audience segment. The audience segment may be refreshed. The event may be synchronized with an external advertising platform.Type: GrantFiled: March 31, 2022Date of Patent: October 24, 2023Assignee: CustomerLabs, Inc.Inventors: Vishnu Vankayala, Vishnu Prasad
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Publication number: 20230317562Abstract: A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Bernd Waidhas, Jan Proschwitz, Stefan Reif, Vishnu Prasad, Georg Seidemann
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Publication number: 20230317544Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.Type: ApplicationFiled: March 21, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230317551Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Vishnu Prasad, Abdallah Bacha, Mohan Prashanth Javare Gowda, Lizabeth Keser, Thomas Wagner, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz
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Publication number: 20230317681Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Sonja Koller, Vishnu Prasad, Bernd Waidhas, Eduardo De Mesa, Lizabeth Keser, Thomas Wagner, Mohan Prashanth Javare Gowda, Abdallah Bacha, Jan Proschwitz
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Publication number: 20230307300Abstract: A semiconductor package comprises a package substrate comprised of comprised of layers of a first material. The semiconductor package includes an integrated circuit (IC) attached to the substrate at a first surface of the IC through a plurality of vias. The semiconductor package includes at least one interface layer comprised of an interface material different from the first material and sealed from exposure to air. The interface material can comprise a moisture-sensitive nonconductive material and can be disposed within the package substrate or between the first surface of the IC and the package substrate, among other locations. Other systems, apparatuses and methods are described.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Inventors: Jan Proschwitz, Stefan Reif, Bernd Waidhas, Vishnu Prasad
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Publication number: 20230299032Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a die having a first conductive contact on a surface; a substrate having a second conductive contact on a surface; and an interconnect electrically coupling the first conductive contact of the die and the second conductive contact of the substrate, wherein the interconnect includes a portion of a nanowire on the second conductive contact and an intermetallic compound (IMC) surrounding at least a portion of the nanowire on the second conductive contact.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Bernd Waidhas, Jan Proschwitz, Stefan Reif, Vishnu Prasad
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Publication number: 20230300975Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230282615Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.Type: ApplicationFiled: March 3, 2022Publication date: September 7, 2023Applicant: Intel CorporationInventors: Thomas Wagner, Abdallah Bacha, Vishnu Prasad, Mohan Prashanth Javare Gowda, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz, Lizabeth Keser
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Patent number: 11394628Abstract: This disclosure describes, in some examples, techniques for improving, adjusting, and/or optimizing the infrastructure of a network. This disclosure also describes techniques for monitoring a network using a ping utility integrated into the monitoring platform described herein at the application service level. This disclosure further describes techniques for monitoring database performance through data collected by, for example, database scripts that capture the response time for queries.Type: GrantFiled: August 24, 2020Date of Patent: July 19, 2022Assignee: Equinix, Inc.Inventors: Vishnu Prasad Chakkassery Vidyadharan, Vaibhav Pralhad Bhosale, Loveneesh Bansal, Greg Alan Ogle
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Patent number: 11126523Abstract: This disclosure describes, in some examples, a monitoring platform to provide integrated system that ingests, correlates, and provides alerts for monitored data relating to nodes, which may include applications, services, containers, and network components. In one example, this disclosure describes a method that includes receiving, by a computing system in a network, criticality information about a node included within the network; identifying, by the computing system, a status change associated with the node; determining, by the computing system and based on the criticality information about the node, an impact resulting from the status change; determining, by the computing system and based on the determined impact, whether to communicate information about the determined impact; and sending, by the computing system, an alert about the determined impact.Type: GrantFiled: January 31, 2020Date of Patent: September 21, 2021Assignee: Equinix, Inc.Inventors: Vishnu Prasad Chakkassery Vidyadharan, Loveneesh Bansal, Vaibhav Pralhad Bhosale, Greg Alan Ogle
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Patent number: 10756990Abstract: This disclosure describes, in some examples, techniques for improving, adjusting, and/or optimizing the infrastructure of a network. This disclosure also describes techniques for monitoring a network using a ping utility integrated into the monitoring platform described herein at the application service level. This disclosure further describes techniques for monitoring database performance through data collected by, for example, database scripts that capture the response time for queries.Type: GrantFiled: November 28, 2017Date of Patent: August 25, 2020Assignee: Equinix, Inc.Inventors: Vishnu Prasad Chakkassery Vidyadharan, Vaibhav Pralhad Bhosale, Loveneesh Bansal, Greg Alan Ogle
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Patent number: 10558541Abstract: This disclosure describes, in some examples, a monitoring platform to provide integrated system that ingests, correlates, and provides alerts for monitored data relating to nodes, which may include applications, services, containers, and network components. In one example, this disclosure describes a method that includes receiving, by a computing system in a network, criticality information about a node included within the network; identifying, by the computing system, a status change associated with the node; determining, by the computing system and based on the criticality information about the node, an impact resulting from the status change; determining, by the computing system and based on the determined impact, whether to communicate information about the determined impact; and sending, by the computing system, an alert about the determined impact.Type: GrantFiled: September 22, 2017Date of Patent: February 11, 2020Assignee: Equinix, Inc.Inventors: Vishnu Prasad Chakkassery Vidyadharan, Loveneesh Bansal, Vaibhav Pralhad Bhosale, Greg Alan Ogle
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Publication number: 20190393125Abstract: Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.Type: ApplicationFiled: June 22, 2018Publication date: December 26, 2019Applicant: Intel IP CorporationInventors: Sonja Koller, Vishnu Prasad, Georg Seidemann
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Publication number: 20180284851Abstract: An electronic component assembly includes a substrate having a first face and an opposed second face. One or more electronic components are coupled with either or both of the first and second faces. A filler interface heat transfer system is coupled with the substrate. The filler interface heat transfer system includes at least one enclosure shell coupled with one of the first or second faces. The at least one enclosure shell surrounds a filler cavity including the one or more electronic components therein. A heat transfer filler is within the filler cavity, the heat transfer filler includes a contoured filler profile conforming to at least the one or more electronic components.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Georg Seidemann, Bernd Waidhas, Thomas Wagner, Andreas Wolter, Sonja Koller, Vishnu Prasad
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Patent number: 10091866Abstract: Discussed generally herein are devices that include a switchable heat path. A device can include a device skin, a circuit board, a plurality of components on the circuit board, and a switchable heat path situated between the components and the device skin, the switchable heat path configured to be switched between an on state and an off state, the switchable heat path configured to conduct a first amount of heat from the components to the device skin when in the on state and configured to conduct a second, lesser amount of heat from the components to the device skin when in an off state.Type: GrantFiled: December 21, 2016Date of Patent: October 2, 2018Assignee: Intel IP CorporationInventors: Sonja Koller, Georg Seidemann, Vishnu Prasad
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Publication number: 20180177037Abstract: Discussed generally herein are devices that include a switchable heat path. A device can include a device skin, a circuit board, a plurality of components on the circuit board, and a switchable heat path situated between the components and the device skin, the switchable heat path configured to be switched between an on state and an off state, the switchable heat path configured to conduct a first amount of heat from the components to the device skin when in the on state and configured to conduct a second, lesser amount of heat from the components to the device skin when in an off state.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Sonja Koller, Georg Seidemann, Vishnu Prasad
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Patent number: 9196047Abstract: A method, system, and computer-readable medium for determining a number of mycobacteria in source image data of a sputum-smear sample are provided. First image data is extracted from the source image data of the sputum-smear sample. Binary image data is created from the extracted first image data. A plurality of groups of blobs is identified in the created binary image data. A distance between a pair of the identified plurality of groups of blobs is determined. If the distance is below a threshold value, the pair is combined as a single group of blobs. The determining is repeated for pairs of the identified plurality of groups of blobs, and the remaining groups of blobs are then classified.Type: GrantFiled: December 23, 2010Date of Patent: November 24, 2015Assignee: MANIPAL INSTITUTE OF TECHNOLOGYInventors: Ramesh R. Galigekere, Rohit Nayak, Vishnu Prasad
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Publication number: 20120177279Abstract: A method, system, and computer-readable medium for determining a number of mycobacteria in source image data of a sputum-smear sample are provided. First image data is extracted from the source image data of the sputum-smear sample. Binary image data is created from the extracted first image data. A plurality of groups of blobs is identified in the created binary image data. A distance between a pair of the identified plurality of groups of blobs is determined. If the distance is below a threshold value, the pair is combined as a single group of blobs. The determining is repeated for pairs of the identified plurality of groups of blobs, and the remaining groups of blobs are then classified.Type: ApplicationFiled: December 23, 2010Publication date: July 12, 2012Inventors: Ramesh R. Galigekere, Rohit Nayak, Vishnu Prasad