Patents by Inventor Vishnu Prasad

Vishnu Prasad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210456
    Abstract: A present chip assembly may have a matrix of dies and cooling devices that may provide active cooling within a package. The cooling devices may provide airflow directed to spaces that are provided between dies placed on a support platform. The placement of the cooling devices may be optimized to provide active cooling at hot spot areas of the package.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Inventors: Eduardo De Mesa, Vishnu Prasad, Bernd Waidhas, Carlton Hanna, Pouya Talebbeydokhti, Jan Proschwitz, Sonja Koller, Stefan Reif
  • Publication number: 20250210428
    Abstract: There may be provided a stiffener assembly for a semiconductor package. The stiffener assembly may include a corner member and a frame member. A primary mating element of the corner member and a secondary mating element of the frame member may be configured to interlock with each other to form a connection joint that permits movement of the secondary mating element relative to the primary mating element.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Inventors: Mohan Prashanth Javare Gowda, Bernd Waidhas, Lizabeth Keser, Cindy Muir, Stephan Stoeckl, Eduardo De Mesa, Stefan Reif, Vishnu Prasad, Georg Seidemann
  • Publication number: 20250201605
    Abstract: The present disclosure relates to an assembly for preventing warpage in a semiconductor package. The assembly may include a semiconductor package substrate including one or more channels arranged longitudinally in an inner core layer of the semiconductor package substrate. The assembly may further include a mount assembly including one or more mounts operable to be insertable into corresponding channels of the semiconductor package substrate.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 19, 2025
    Inventors: Sonja Koller, Pouya Talebbeydokhti, Vishnu Prasad, Stefan Reif, Carlton Hanna, Thomas Wagner
  • Publication number: 20250201622
    Abstract: A semiconductor tool having a support assembly for holding a semiconductor panel in a level position during an assembly process is able to remediate the warpage that may be present in the semiconductor panel. The support assembly may be equipped with a plurality of height-adjustable support pillars in the form of an array that is positioned below the semiconductor panel to provide a level position. The support pillars may be activated by a controller to engage or land on dedicated landing features or pads formed on the semiconductor panel or on suitable landing features that may be found in a semiconductor design layout and provide a dual use.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 19, 2025
    Inventors: Sonja Koller, Pouya Talebbeydokhti, Vishnu Prasad, Stefan Reif, Carlton Hanna, Thomas Wagner
  • Patent number: 12249553
    Abstract: Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 11, 2025
    Assignee: Intel Corporation
    Inventors: Sonja Koller, Vishnu Prasad, Georg Seidemann
  • Publication number: 20240395655
    Abstract: In one embodiment, an integrated circuit package includes a package substrate, a first integrated circuit die electrically coupled to the package substrate via wire bond connectors, and a second integrated circuit die coupled to the package substrate. The package further includes a heat spreader coupled to the first integrated circuit die via a thermal interface material (TIM) and a dielectric material encompassing the first integrated circuit die and the second integrated circuit die on the package substrate. A top surface of the heat spreader is aligned with a top surface of the dielectric material.
    Type: Application
    Filed: May 26, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Avi Tsarfati, David T. O’Sullivan, Vishnu Prasad, Thomas Wagner, Aruna Manoharan
  • Patent number: 11798037
    Abstract: Advertising audience segment creators, including methods, systems, and apparatuses for automated creation of audience segments in advertising platforms are disclosed herein. Data may be received at a processor of an application server from a remote device. The data may be related to a user of the remote device. An audience member may be retrieved from an audience database. The audience member may correspond to an external identifier of the user. The audience database may be stored on an electronic storage device. The audience member may be assigned to an event. The assigning of the audience member to the event may be based on the data. Assigning the audience member to the event may be based on a refresh interval. The refresh interval may be of an audience segment. The audience segment may be refreshed. The event may be synchronized with an external advertising platform.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: October 24, 2023
    Assignee: CustomerLabs, Inc.
    Inventors: Vishnu Vankayala, Vishnu Prasad
  • Publication number: 20230317551
    Abstract: Disclosed herein are microelectronics packages that include thermal pillars for at least localized extraction of generated heat and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies stacked on the substrate with at least one of the plurality of dies connected to the substrate. A heat spreader may be located proximate at least a portion of the plurality of dies. Respective thermal pillars from a plurality of thermal pillars may extend from at least one of the plurality dies to the heat spreader. Each of the plurality of thermal pillars may define a respective pathway from at least one of the plurality of dies to the heat spreader.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Vishnu Prasad, Abdallah Bacha, Mohan Prashanth Javare Gowda, Lizabeth Keser, Thomas Wagner, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz
  • Publication number: 20230317544
    Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.
    Type: Application
    Filed: March 21, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
  • Publication number: 20230317681
    Abstract: Disclosed herein are microelectronic packages having thermally conductive layers and methods for manufacturing the same. The microelectronics packages may include a substrate and a plurality of dies connected to the substrate and/or each other to form a die stack. The dies may have a perimeter. A thermally conductive layer may be located in between the respective dies. The thermally conductive layers may extend past at least a portion of the perimeters, thereby providing enhanced cooling of the die stack.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Sonja Koller, Vishnu Prasad, Bernd Waidhas, Eduardo De Mesa, Lizabeth Keser, Thomas Wagner, Mohan Prashanth Javare Gowda, Abdallah Bacha, Jan Proschwitz
  • Publication number: 20230317562
    Abstract: A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Bernd Waidhas, Jan Proschwitz, Stefan Reif, Vishnu Prasad, Georg Seidemann
  • Publication number: 20230307300
    Abstract: A semiconductor package comprises a package substrate comprised of comprised of layers of a first material. The semiconductor package includes an integrated circuit (IC) attached to the substrate at a first surface of the IC through a plurality of vias. The semiconductor package includes at least one interface layer comprised of an interface material different from the first material and sealed from exposure to air. The interface material can comprise a moisture-sensitive nonconductive material and can be disposed within the package substrate or between the first surface of the IC and the package substrate, among other locations. Other systems, apparatuses and methods are described.
    Type: Application
    Filed: March 28, 2022
    Publication date: September 28, 2023
    Inventors: Jan Proschwitz, Stefan Reif, Bernd Waidhas, Vishnu Prasad
  • Publication number: 20230299032
    Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a die having a first conductive contact on a surface; a substrate having a second conductive contact on a surface; and an interconnect electrically coupling the first conductive contact of the die and the second conductive contact of the substrate, wherein the interconnect includes a portion of a nanowire on the second conductive contact and an intermetallic compound (IMC) surrounding at least a portion of the nanowire on the second conductive contact.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Applicant: Intel Corporation
    Inventors: Bernd Waidhas, Jan Proschwitz, Stefan Reif, Vishnu Prasad
  • Publication number: 20230300975
    Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 21, 2023
    Applicant: Intel Corporation
    Inventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
  • Publication number: 20230282615
    Abstract: A microelectronic assembly is provided, comprising: an interposer having a first side and a second side opposite to the first side; a plurality of integrated circuit (IC) dies in a plurality of layers on the first side of the interposer, the plurality of IC dies being encased by a dielectric material; a package substrate on the second side of the interposer; a plurality of conductive vias through the plurality of layers; and redistribution layers adjacent to the layers in the plurality of layers, at least some of the redistribution layers comprising conductive traces coupling the conductive vias to the IC dies.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Applicant: Intel Corporation
    Inventors: Thomas Wagner, Abdallah Bacha, Vishnu Prasad, Mohan Prashanth Javare Gowda, Bernd Waidhas, Sonja Koller, Eduardo De Mesa, Jan Proschwitz, Lizabeth Keser
  • Patent number: 11394628
    Abstract: This disclosure describes, in some examples, techniques for improving, adjusting, and/or optimizing the infrastructure of a network. This disclosure also describes techniques for monitoring a network using a ping utility integrated into the monitoring platform described herein at the application service level. This disclosure further describes techniques for monitoring database performance through data collected by, for example, database scripts that capture the response time for queries.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 19, 2022
    Assignee: Equinix, Inc.
    Inventors: Vishnu Prasad Chakkassery Vidyadharan, Vaibhav Pralhad Bhosale, Loveneesh Bansal, Greg Alan Ogle
  • Patent number: 11126523
    Abstract: This disclosure describes, in some examples, a monitoring platform to provide integrated system that ingests, correlates, and provides alerts for monitored data relating to nodes, which may include applications, services, containers, and network components. In one example, this disclosure describes a method that includes receiving, by a computing system in a network, criticality information about a node included within the network; identifying, by the computing system, a status change associated with the node; determining, by the computing system and based on the criticality information about the node, an impact resulting from the status change; determining, by the computing system and based on the determined impact, whether to communicate information about the determined impact; and sending, by the computing system, an alert about the determined impact.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: September 21, 2021
    Assignee: Equinix, Inc.
    Inventors: Vishnu Prasad Chakkassery Vidyadharan, Loveneesh Bansal, Vaibhav Pralhad Bhosale, Greg Alan Ogle
  • Patent number: 10756990
    Abstract: This disclosure describes, in some examples, techniques for improving, adjusting, and/or optimizing the infrastructure of a network. This disclosure also describes techniques for monitoring a network using a ping utility integrated into the monitoring platform described herein at the application service level. This disclosure further describes techniques for monitoring database performance through data collected by, for example, database scripts that capture the response time for queries.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 25, 2020
    Assignee: Equinix, Inc.
    Inventors: Vishnu Prasad Chakkassery Vidyadharan, Vaibhav Pralhad Bhosale, Loveneesh Bansal, Greg Alan Ogle
  • Patent number: 10558541
    Abstract: This disclosure describes, in some examples, a monitoring platform to provide integrated system that ingests, correlates, and provides alerts for monitored data relating to nodes, which may include applications, services, containers, and network components. In one example, this disclosure describes a method that includes receiving, by a computing system in a network, criticality information about a node included within the network; identifying, by the computing system, a status change associated with the node; determining, by the computing system and based on the criticality information about the node, an impact resulting from the status change; determining, by the computing system and based on the determined impact, whether to communicate information about the determined impact; and sending, by the computing system, an alert about the determined impact.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 11, 2020
    Assignee: Equinix, Inc.
    Inventors: Vishnu Prasad Chakkassery Vidyadharan, Loveneesh Bansal, Vaibhav Pralhad Bhosale, Greg Alan Ogle
  • Publication number: 20190393125
    Abstract: Present disclosure relates to IC packages with integrated thermal contacts. In some embodiments, an IC package includes a package substrate, an IC die that is coupled to the package substrate, and at least one thermal contact for coupling to at least a portion of a heat exchanger, where the thermal contact is limited to being in a region located at a periphery of the IC package. In some embodiments, thermal contacts are such that at least a portion of a heat exchanger is to be attached on the side of the IC package. In some embodiments, thermal contacts may be provided within a recessed portion at the periphery of the IC package. Providing a thermal contact at a periphery of an IC package may enable improved cooling options, especially for systems where there is no or limited space for providing conventional heat exchangers on the top of the package.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Applicant: Intel IP Corporation
    Inventors: Sonja Koller, Vishnu Prasad, Georg Seidemann