Abstract: A device includes a communication interface, a command processing circuit, a clock synchronization circuit, and a controllable clock source. The command processing circuit has a command input, a reference frequency output, and a reference phase output. The command input is coupled to the communication interface. The clock synchronization circuit has a reference frequency input, a reference phase input, and a frequency control output. The reference frequency output is coupled to the reference frequency input, and the reference phase input coupled to the reference phase output. The clock synchronization circuit includes a frequency synchronization circuit and a phase synchronization circuit. The controllable clock source has a frequency control input and a clock output. The frequency control input is coupled to the frequency control output.

Abstract: An example system includes: a first device having a ground plane at a first voltage, a first transmission terminal, and a second transmission terminal; a second device having a ground plane at a second voltage, a first receiver terminal, and a second receiver terminal; wherein the first device is configured to: operate in either a linear mode or a saturation mode based on a magnitude of electromagnetic interference; and during the linear mode or the saturation mode, use the first transmission terminal and second transmission terminal to transmit a differential signal to the second device.

Abstract: A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.

Abstract: An oscillator circuit includes a ring oscillator and a ramp generator. The ring oscillator includes a first inverter and a second inverter. The first inverter has and a first inverter input, a first inverter output, and a first power terminal. The second inverter has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output and the second inverter output is coupled to the first inverter input. The ramp generator circuit has a ramp output coupled to the first power terminal and the second power terminal.

Abstract: An integrated circuit (IC) includes an oscillator circuit having a control input. A control circuit has a control output coupled to the control input. The control circuit is configured to generate a control signal to the control input of the oscillator circuit to cause: the oscillator circuit to be configured as a frequency-locked loop in response to the control signal being in a first state; and the oscillator circuit to be configured as a phase-locked loop in response to the control signal being in a second state.

Abstract: An oscillator circuit includes a ring oscillator and a ramp generator. The ring oscillator includes a first inverter and a second inverter. The first inverter has and a first inverter input, a first inverter output, and a first power terminal. The second inverter has a second inverter input, a second inverter output, and a second power terminal. The second inverter input is coupled to the first inverter output and the second inverter output is coupled to the first inverter input. The ramp generator circuit has a ramp output coupled to the first power terminal and the second power terminal.

Abstract: An apparatus comprises a plurality of analog front ends (AFEs) adapted to be coupled to a plurality of battery cells and configured to decrease voltages received from the plurality of battery cells to produce a plurality of AFE voltages. The apparatus further comprises at least one analog-to-digital converter (ADC) coupled to the plurality of AFEs and configured to convert the plurality of AFE voltages to a plurality of corresponding digital signals. The apparatus also comprises a plurality of digital channel registers coupled to the at least one ADC and configured to store the plurality of digital signals, and a processor coupled to the at least one ADC and configured to adjust, in a round-robin calculation scheme, the plurality of digital signals based on a plurality of common mode voltage values and a plurality of common mode to differential gain values associated with the plurality of AFEs.

Abstract: A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.

Abstract: An electronic device includes an ADC, a multiplexer, a voltage reference circuit, an analog circuit, and a digital circuit. The ADC has a signal input, a reference input, and an output. The multiplexer has signal inputs and a signal output coupled to the signal input of the ADC. The voltage reference circuit has an output coupled to the reference input of the ADC, a first strain sensor coupled to a first signal input of the multiplexer, a second strain sensor coupled to a second signal input of the multiplexer, and a temperature sensor. The analog circuit has an input coupled to a battery, and an output coupled to a fourth signal input of the multiplexer. The digital circuit is coupled to the output of the ADC and stores correction parameters for correcting a converted battery voltage value from the ADC.

Abstract: An electronic device includes an ADC, a multiplexer, a voltage reference circuit, an analog circuit, and a digital circuit. The ADC has a signal input, a reference input, and an output. The multiplexer has signal inputs and a signal output coupled to the signal input of the ADC. The voltage reference circuit has an output coupled to the reference input of the ADC, a first strain sensor coupled to a first signal input of the multiplexer, a second strain sensor coupled to a second signal input of the multiplexer, and a temperature sensor. The analog circuit has an input coupled to a battery, and an output coupled to a fourth signal input of the multiplexer. The digital circuit is coupled to the output of the ADC and stores correction parameters for correcting a converted battery voltage value from the ADC.

Abstract: An apparatus comprises a plurality of analog front ends (AFEs) adapted to be coupled to a plurality of battery cells and configured to decrease voltages received from the plurality of battery cells to produce a plurality of AFE voltages. The apparatus further comprises at least one analog-to-digital converter (ADC) coupled to the plurality of AFEs and configured to convert the plurality of AFE voltages to a plurality of corresponding digital signals. The apparatus also comprises a plurality of digital channel registers coupled to the at least one ADC and configured to store the plurality of digital signals, and a processor coupled to the at least one ADC and configured to adjust, in a round-robin calculation scheme, the plurality of digital signals based on a plurality of common mode voltage values and a plurality of common mode to differential gain values associated with the plurality of AFEs.

Abstract: A battery-operated device comprises: a first battery cell having a voltage; a second battery cell having a voltage; a first anti-aliasing filter operable to be coupled to the first battery cell; a second anti-aliasing filter operable to be coupled to the second battery cell; an analog-to-digital converter operable to be coupled to the first anti-aliasing filter during a first period of time or the second anti-aliasing filter during a second period of time different than the first period of time; and wherein the second anti-aliasing filter is charged during the first period of time and the first anti-aliasing filter is charged during the second period of time.

Abstract: A battery-operated device comprises: a first battery cell having a voltage; a second battery cell having a voltage; a first anti-aliasing filter operable to be coupled to the first battery cell; a second anti-aliasing filter operable to be coupled to the second battery cell; an analog-to-digital converter operable to be coupled to the first anti-aliasing filter during a first period of time or the second anti-aliasing filter during a second period of time different than the first period of time; and wherein the second anti-aliasing filter is charged during the first period of time and the first anti-aliasing filter is charged during the second period of time.

Abstract: A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.

Abstract: A voltage protection circuit, comprising a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to a first node, a source terminal coupled to a second node, and a drain terminal coupled to a third node, a second MOSFET having a gate terminal coupled to the first node, a source terminal coupled to the second node, and a drain terminal coupled to a fourth node, a first current mirror coupled to the third node and configured to couple to a fifth node, a sixth node, and a regulator supply, and a second current mirror coupled to the fourth node, and configured to couple to the fifth node, the sixth node, and a ground node.

Abstract: A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.

Abstract: A voltage protection circuit, comprising a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to a first node, a source terminal coupled to a second node, and a drain terminal coupled to a third node, a second MOSFET having a gate terminal coupled to the first node, a source terminal coupled to the second node, and a drain terminal coupled to a fourth node, a first current mirror coupled to the third node and configured to couple to a fifth node, a sixth node, and a regulator supply, and a second current mirror coupled to the fourth node, and configured to couple to the fifth node, the sixth node, and a ground node.

Abstract: Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.

Abstract: Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.

Abstract: In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.