Patents by Inventor Vishnu Ravinuthula
Vishnu Ravinuthula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072818Abstract: A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventor: Vishnu RAVINUTHULA
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Patent number: 11536773Abstract: An electronic device includes an ADC, a multiplexer, a voltage reference circuit, an analog circuit, and a digital circuit. The ADC has a signal input, a reference input, and an output. The multiplexer has signal inputs and a signal output coupled to the signal input of the ADC. The voltage reference circuit has an output coupled to the reference input of the ADC, a first strain sensor coupled to a first signal input of the multiplexer, a second strain sensor coupled to a second signal input of the multiplexer, and a temperature sensor. The analog circuit has an input coupled to a battery, and an output coupled to a fourth signal input of the multiplexer. The digital circuit is coupled to the output of the ADC and stores correction parameters for correcting a converted battery voltage value from the ADC.Type: GrantFiled: July 30, 2021Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jose Antonio Vieira Formenti, Michael Szelong, Takao Oshida, Tobias Bernhard Fritz, Vishnu Ravinuthula
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Publication number: 20220187378Abstract: An electronic device includes an ADC, a multiplexer, a voltage reference circuit, an analog circuit, and a digital circuit. The ADC has a signal input, a reference input, and an output. The multiplexer has signal inputs and a signal output coupled to the signal input of the ADC. The voltage reference circuit has an output coupled to the reference input of the ADC, a first strain sensor coupled to a first signal input of the multiplexer, a second strain sensor coupled to a second signal input of the multiplexer, and a temperature sensor. The analog circuit has an input coupled to a battery, and an output coupled to a fourth signal input of the multiplexer. The digital circuit is coupled to the output of the ADC and stores correction parameters for correcting a converted battery voltage value from the ADC.Type: ApplicationFiled: July 30, 2021Publication date: June 16, 2022Applicant: Texas Instruments IncorporatedInventors: Jose Antonio Vieira Formenti, Michael Szelong, Takao Oshida, Tobias Bernhard Fritz, Vishnu Ravinuthula
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Publication number: 20210278474Abstract: An apparatus comprises a plurality of analog front ends (AFEs) adapted to be coupled to a plurality of battery cells and configured to decrease voltages received from the plurality of battery cells to produce a plurality of AFE voltages. The apparatus further comprises at least one analog-to-digital converter (ADC) coupled to the plurality of AFEs and configured to convert the plurality of AFE voltages to a plurality of corresponding digital signals. The apparatus also comprises a plurality of digital channel registers coupled to the at least one ADC and configured to store the plurality of digital signals, and a processor coupled to the at least one ADC and configured to adjust, in a round-robin calculation scheme, the plurality of digital signals based on a plurality of common mode voltage values and a plurality of common mode to differential gain values associated with the plurality of AFEs.Type: ApplicationFiled: March 5, 2021Publication date: September 9, 2021Inventors: Vishnu RAVINUTHULA, Takao OSHIDA, Geoffrey GRIMMER
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Patent number: 10855307Abstract: A battery-operated device comprises: a first battery cell having a voltage; a second battery cell having a voltage; a first anti-aliasing filter operable to be coupled to the first battery cell; a second anti-aliasing filter operable to be coupled to the second battery cell; an analog-to-digital converter operable to be coupled to the first anti-aliasing filter during a first period of time or the second anti-aliasing filter during a second period of time different than the first period of time; and wherein the second anti-aliasing filter is charged during the first period of time and the first anti-aliasing filter is charged during the second period of time.Type: GrantFiled: March 5, 2020Date of Patent: December 1, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vishnu Ravinuthula, Kyl Scott
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Publication number: 20200204191Abstract: A battery-operated device comprises: a first battery cell having a voltage; a second battery cell having a voltage; a first anti-aliasing filter operable to be coupled to the first battery cell; a second anti-aliasing filter operable to be coupled to the second battery cell; an analog-to-digital converter operable to be coupled to the first anti-aliasing filter during a first period of time or the second anti-aliasing filter during a second period of time different than the first period of time; and wherein the second anti-aliasing filter is charged during the first period of time and the first anti-aliasing filter is charged during the second period of time.Type: ApplicationFiled: March 5, 2020Publication date: June 25, 2020Inventors: Vishnu RAVINUTHULA, Kyl SCOTT
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Publication number: 20200136642Abstract: A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.Type: ApplicationFiled: October 29, 2018Publication date: April 30, 2020Inventors: Vishnu RAVINUTHULA, Kyl Wayne SCOTT
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Patent number: 10630072Abstract: A voltage protection circuit, comprising a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to a first node, a source terminal coupled to a second node, and a drain terminal coupled to a third node, a second MOSFET having a gate terminal coupled to the first node, a source terminal coupled to the second node, and a drain terminal coupled to a fourth node, a first current mirror coupled to the third node and configured to couple to a fifth node, a sixth node, and a regulator supply, and a second current mirror coupled to the fourth node, and configured to couple to the fifth node, the sixth node, and a ground node.Type: GrantFiled: December 28, 2017Date of Patent: April 21, 2020Assignee: Texas Instruments IncorporatedInventors: Vishnu Ravinuthula, Simon Bevan Churchill, Mark Allen Hamlett, Eric Rudeen
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Patent number: 10623013Abstract: A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.Type: GrantFiled: October 29, 2018Date of Patent: April 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vishnu Ravinuthula, Kyl Wayne Scott
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Publication number: 20190207384Abstract: A voltage protection circuit, comprising a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal coupled to a first node, a source terminal coupled to a second node, and a drain terminal coupled to a third node, a second MOSFET having a gate terminal coupled to the first node, a source terminal coupled to the second node, and a drain terminal coupled to a fourth node, a first current mirror coupled to the third node and configured to couple to a fifth node, a sixth node, and a regulator supply, and a second current mirror coupled to the fourth node, and configured to couple to the fifth node, the sixth node, and a ground node.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Vishnu RAVINUTHULA, Simon Bevan CHURCHILL, Mark Allen HAMLETT, Eric RUDEEN
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Patent number: 9543969Abstract: Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.Type: GrantFiled: December 7, 2015Date of Patent: January 10, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vishnu Ravinuthula, Kenneth George Maclean
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Publication number: 20160164405Abstract: Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.Type: ApplicationFiled: December 7, 2015Publication date: June 9, 2016Inventors: Vishnu Ravinuthula, Kenneth George Maclean
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Patent number: 8964880Abstract: In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.Type: GrantFiled: July 11, 2012Date of Patent: February 24, 2015Assignee: Texas Instruments IncorporatedInventors: Vishnu Ravinuthula, Dushmantha Rajapaksha, Hugh Mair
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Publication number: 20140016718Abstract: In an embodiment of the invention, a frequency divider in a PLL (phase-locked loop) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first DC (direct current) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.Type: ApplicationFiled: July 11, 2012Publication date: January 16, 2014Applicant: Texas Instruments IncorporatedInventors: Vishnu Ravinuthula, Dushmantha Rajapaksha, Hugh Mair
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Patent number: 8508304Abstract: Reducing a gain of a VCO, which may be used in a serdes system, includes using an oscillator replicating the VCO. The oscillator frequency varies according to PVT conditions of circuit elements of the oscillator, which affect a speed of the circuit elements. A first circuit receives an output of the oscillator to produce a current that varies inversely proportionally to the oscillator frequency. A second circuit injects the current into a power supply line of the VCO. Thus, high VCO frequencies can be attained. By reducing the gain of the VCO, thermal noise contribution of the loop resistor and the loop capacitor required for desired loop bandwidth are reduced. During fast corner conditions, minimal current is injected into the VCO. During slow corner conditions, high current is injected into the VCO. These help keep VCTRL of the PLL loop close to a mid-rail operating region.Type: GrantFiled: October 17, 2011Date of Patent: August 13, 2013Assignee: Texas Instruments IncorporatedInventor: Vishnu Ravinuthula
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Publication number: 20130093526Abstract: Reducing a gain of a VCO, which may be used in a serdes system, includes using an oscillator replicating the VCO. The oscillator frequency varies according to PVT conditions of circuit elements of the oscillator, which affect a speed of the circuit elements. A first circuit receives an output of the oscillator to produce a current that varies inversely proportionally to the oscillator frequency. A second circuit injects the current into a power supply line of the VCO. Thus, high VCO frequencies can be attained. By reducing the gain of the VCO, thermal noise contribution of the loop resistor and the loop capacitor required for desired loop bandwidth are reduced. During fast corner conditions, minimal current is injected into the VCO. During slow corner conditions, high current is injected into the VCO. These help keep VCTRL of the PLL loop close to a mid-rail operating region.Type: ApplicationFiled: October 17, 2011Publication date: April 18, 2013Applicant: Texas Instruments IncorporatedInventor: Vishnu Ravinuthula
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Publication number: 20050231398Abstract: A time-mode analog computation circuit is provided. The time-mode analog computation circuit includes one or more inputs for receiving one or more temporal input signals. The time-mode analog computation circuit further includes circuitry for performing a mathematical operation based on the one or more temporal input signals. A result of the mathematical operation is expressed in a timing of an output signal generated by the circuit.Type: ApplicationFiled: April 12, 2005Publication date: October 20, 2005Applicant: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.Inventors: Vishnu Ravinuthula, John Harris, Jose Fortes