Patents by Inventor Vishram Pandit

Vishram Pandit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital linear regulator clamping method and apparatus
    Patent number: 11429172
    Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Alexander Uan-Zo-Li, Eugene Gorbatov, Harish Krishnamurthy, Alexander Lyakhov, Patrick Leung, Stephen Gunther, Arik Gihon, Khondker Ahmed, Philip Lehwalder, Sameer Shekhar, Vishram Pandit, Nimrod Angel, Michael Zelikson
  • DIGITAL LINEAR REGULATOR CLAMPING METHOD AND APPARATUS
    Publication number: 20210208656
    Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Applicant: Intel Corporation
    Inventors: Alexander Uan-Zo-Li, Eugene Gorbatov, Harish Krishnamurthy, Alexander Lyakhov, Patrick Leung, Stephen Gunther, Arik Gihon, Khondker Ahmed, Philip Lehwalder, Sameer Shekhar, Vishram Pandit, Nimrod Angel, Michael Zelikson