Patents by Inventor Vishrut VAIBHAV

Vishrut VAIBHAV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087078
    Abstract: Methods, devices, and systems for rendering primitives in a frame. During a visibility pass, state packets are processed to determine a register state, and the register state is stored in a memory device. During a rendering pass, the state packets are discarded and the register state is read from the memory device. In some implementations, a graphics pipeline is configured during the visibility pass based on the register state determined by processing the state packets, and the graphics pipeline is configured during the rendering pass based on the register state read from the memory device. In some implementations, replay control packets, draw packets, and the state packets, from a packet stream, are processed during the visibility pass; the draw packets are modified based on visibility information determined during the visibility pass; and the replay control packets and draw packets are processed, during the rendering pass.
    Type: Application
    Filed: June 19, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander Fuad Ashkar, Vishrut Vaibhav, Manu Rastogi, Harry J. Wise
  • Publication number: 20240070961
    Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.
    Type: Application
    Filed: December 27, 2022
    Publication date: February 29, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael John Livesley, Vishrut Vaibhav, Tad Robert Litwiller
  • Patent number: 11527033
    Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: December 13, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Saad Arrabi, Vishrut Vaibhav, Mangesh P. Nijasure, Todd Martin
  • Publication number: 20210295585
    Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Inventors: Saad ARRABI, Vishrut VAIBHAV, Mangesh P. NIJASURE, Todd MARTIN