Patents by Inventor Vishwanath Bhat
Vishwanath Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11540649Abstract: A carry handle includes a shoulder strap and strap anchors at opposite ends of the shoulder strap. Each strap anchor can be mated to one end of an object to be carried to allow a user to wear the carry handle in an over-the-shoulder manner. The carry handle can be coupled to an infant carrier for use by a caregiver during transport of the infant carrier.Type: GrantFiled: April 14, 2021Date of Patent: January 3, 2023Assignee: Dorel Juvenile Group, Inc.Inventors: Vishwanath Bhat, Nathan W. Heisey, Devin J. Coakley
-
Publication number: 20210315394Abstract: A carry handle includes a shoulder strap and strap anchors at opposite ends of the shoulder strap. Each strap anchor can be mated to one end of an object to be carried to allow a user to wear the carry handle in an over-the-shoulder manner. The carry handle can be coupled to an infant carrier for use by a caregiver during transport of the infant carrier.Type: ApplicationFiled: April 14, 2021Publication date: October 14, 2021Inventors: Vishwanath BHAT, Nathan W. HEISEY, Devin J. COAKLEY
-
Patent number: 11050020Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: May 8, 2020Date of Patent: June 29, 2021Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Patent number: 10879462Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: May 8, 2020Date of Patent: December 29, 2020Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Publication number: 20200274059Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Publication number: 20200274060Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Patent number: 10665782Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: August 23, 2018Date of Patent: May 26, 2020Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Patent number: 10658580Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: December 29, 2017Date of Patent: May 19, 2020Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Patent number: 10556688Abstract: A latch assembly (110) can include a latch rail (314), a latch body (312), and a biasing mechanism (322). The latch rail can include a first end (318) and a second end. The first end can couple to a back portion of a seat that includes a table body. The latch body (312) can couple to the second end of the latch rail (314) such that the latch body can move between a first position and a second position relative to the latch rail. The latch body can prevent the table body from moving between a stowed position and a stowed position while in the first position. The latch body can allow the table body to move between the stowed position and the deployed position in the second position. The biasing mechanism (322) can couple to the latch body (312) and can bias the latch body into the first position.Type: GrantFiled: June 3, 2016Date of Patent: February 11, 2020Assignee: Safran Seats USA LLCInventors: Vishwanath Bhat, Christopher M. Gumbleton, Mark Carpenter
-
Patent number: 10249819Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: GrantFiled: April 3, 2014Date of Patent: April 2, 2019Assignee: Micron Technology, Inc.Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Publication number: 20180366645Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: August 23, 2018Publication date: December 20, 2018Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Publication number: 20180194477Abstract: A latch assembly (110) can include a latch rail (314), a latch body (312), and a biasing mechanism (322). The latch rail can include a first end (318) and a second end. The first end can couple to a back portion of a seat that includes a table body. The latch body (312) can couple to the second end of the latch rail (314) such that the latch body can move between a first position and a second position relative to the latch rail. The latch body can prevent the table body from moving between a stowed position and a stowed position while in the first position. The latch body can allow the table body to move between the stowed position and the deployed position in the second position. The biasing mechanism (322) can couple to the latch body (312) and can bias the latch body into the first position.Type: ApplicationFiled: June 3, 2016Publication date: July 12, 2018Applicant: Zodiac Seats US LLCInventors: Vishwanath Bhat, Christopher M. Gumbleton, Mark Carpenter
-
Patent number: 10008381Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.Type: GrantFiled: October 30, 2015Date of Patent: June 26, 2018Assignee: Micron Technology, Inc.Inventors: Nik Mirin, Tsai-Yu Huang, Vishwanath Bhat, Chris M. Carlson, Vassil N. Antonov
-
Publication number: 20180123036Abstract: A method of forming a semiconductor structure. The method comprises forming a protective portion of a liner on at least a portion of stack structures on a substrate. The protective portion comprises a material formulated to adhere to the stack structures. A conformal portion of the liner is formed on the protective portion of the liner or on the protective portion of the liner and exposed materials of the stack structures. At least one of the protective portion and the conformal portion does not comprise aluminum. Additional methods of forming a semiconductor structure are disclosed, as are semiconductor structures including the liners comprising the protective portion and the conformal portion.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Kyle B. Campbell, Irina Vasilyeva, Farrell M. Good, Vishwanath Bhat, Kyuchul Chong
-
Patent number: 9887083Abstract: A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO2 and the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuO2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.Type: GrantFiled: October 7, 2015Date of Patent: February 6, 2018Assignee: Micron Technology, Inc.Inventors: Vassil N. Antonov, Vishwanath Bhat
-
Patent number: 9701229Abstract: Described are arm rest stop assemblies including an arm rest pivotally coupled to a fixed portion of a passenger seat and a down-stop mechanism comprising an adjustment pin inserted through the fixed portion of the passenger seat and an adjustment fastener coupled to the adjustment pin and the fixed portion of the passenger seat, wherein the location of the adjustment pin does not present a pinch point for passengers when the arm rest is lowered to the deployed position.Type: GrantFiled: April 24, 2013Date of Patent: July 11, 2017Assignee: Zodiac Seats US LLCInventors: Vishwanath Bhat, Ray Napier, Robert Bernal
-
Patent number: 9627501Abstract: Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.Type: GrantFiled: January 28, 2015Date of Patent: April 18, 2017Assignee: Micron Technology, Inc.Inventors: F. Daniel Gealy, Vishwanath Bhat, Cancheepuram V. Srividya, M. Noel Rocklein
-
Patent number: 9466660Abstract: A semiconductor structure may include a first electrode over a substrate, a high-K dielectric material over the first electrode, and a second electrode over the high-K dielectric material, wherein at least one of the first electrode and the second electrode may include a material selected from the group consisting of a molybdenum nitride (MoaNb) material, a molybdenum oxynitride (MoOxNy) material, a molybdenum oxide (MoOx) material, and a molybdenum-based alloy material comprising molybdenum and nitrogen.Type: GrantFiled: October 16, 2013Date of Patent: October 11, 2016Assignee: Micron Technology, Inc.Inventors: Matthew N. Rocklein, Kotha Sai Madhukar Reddy, Vassil Antonov, Vishwanath Bhat
-
Patent number: 9397143Abstract: Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a substrate, an array of phase change memory (PCM) elements disposed on the substrate, wherein individual PCM elements of the array of PCM elements comprise a chalcogenide material and a liner disposed on sidewall surfaces of the individual PCM elements, wherein the liner comprises aluminum (Al), silicon (Si) and oxygen (O). Other embodiments may be described and/or claimed.Type: GrantFiled: December 20, 2013Date of Patent: July 19, 2016Assignee: Intel CorporationInventors: Noel Rocklein, Qian Tao, Zhe Song, Vishwanath Bhat
-
Publication number: 20160056038Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.Type: ApplicationFiled: October 30, 2015Publication date: February 25, 2016Inventors: Nik Mirin, Tsai-Yu Huang, Vishwanath Bhat, Chris M. Carlson, Vassil N. Antonov