Patents by Inventor Vishwani D. Agrawal
Vishwani D. Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210318379Abstract: The methods and systems are directed to automated computer analysis and machine learning. Specifically, the systems and methods for using machine learning to generate fault prediction models and applying the fault prediction models to logical circuits to optimize test point insertion determinations and optimize fault detection in the logical circuit. Disclosed are methods and systems that that generates training data from training circuits (and optionally generate training circuits), trains a learning segment (which may include an artificial neural network (ANN)) using the training data. The learning segment (once trained) generates fault prediction models to predict the quality of a TP inserted on a given circuit location and optimize TPI for a given circuit. The methods and systems described provide computational (CPU/processing) time advantages and precision over conventional methods.Type: ApplicationFiled: April 9, 2021Publication date: October 14, 2021Applicant: Auburn UniversityInventors: Spencer Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal
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Patent number: 6131181Abstract: The present invention relates to a method and system for identifying tested path-delay faults in integrated circuits. A path status graph is generated to represent the detected status of simulated path-delay faults. The path status graph includes vertices representing primary inputs, primary outputs and elements of the circuit. Detected status path-delay faults can be dynamically distributed to edges of the path status graph. Tested path-delay faults can be identified from traversal of the edges of the path status graph.Type: GrantFiled: October 23, 1997Date of Patent: October 10, 2000Assignee: Rutgers UniversityInventors: Michael Bushnell, Marwan A. Gharaybeh, Vishwani D. Agrawal
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Patent number: 5657240Abstract: Techniques for the generation of tests for detecting specified faults in circuits that include non-Boolean components and for identifying these undetectable faults that are logically redundant. The main features are: (1) only one Boolean variable is used to represent the value on a signal and all signals assume only Boolean values during the test generation procedure, (2) function of non-Boolean components is separated into Boolean and non-Boolean states, and energy functions are derived only for the Boolean state, and (3) non-Boolean states are implicitly considered in the energy minimization procedure.Type: GrantFiled: May 1, 1995Date of Patent: August 12, 1997Assignee: NEC USA, Inc.Inventors: Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal
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Patent number: 5606567Abstract: High speed testing of a digital circuit may be performed although the rated frequency of the circuit exceeds the frequency capability of the test equipment. A digital circuit may be designed such that a controllable delay may be introduced in the timing paths of the circuit during testing using test stimuli which are applied at a clock rate that is less than the rated frequency of the circuit. By adding delay to the combinational signal path, testing of the circuit for operation at the maximum operating frequency is achieved during testing at a clock rate which is within the capability of the test equipment. The controllable delay may be incorporated as a delay element into a single-clock circuit and controlled by manipulation of the duty-cycle of a clock waveform which is applied to the circuit. The delay circuit is so designed that its function is also testable. In a multi-clock circuit, the delay is added to the circuit by skewing one clock signal with respect to the other clock signals.Type: GrantFiled: October 21, 1994Date of Patent: February 25, 1997Assignee: Lucent Technologies Inc.Inventors: Vishwani D. Agrawal, Tapan J. Chakraborty
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Patent number: 5590135Abstract: A method for testing a sequential circuit by applying a number of test vectors to the primary inputs of the sequential circuit between each application of a clock circuit. Once the sequential circuit enters a state and that state is a necessary condition for detecting various faults, test vectors are applied to the primary inputs of the sequential circuit, which vectors are designed to propagate all fault effects that can be propagated at that state of the circuit. Once those vectors have been applied, a state-advancing vector is applied immediately before the application of the clock. The state-advancing vector is designed to condition the circuit to allow more fault effects to be propagated to the primary outputs, and to propagate fault effects into the storage elements of the circuit.Type: GrantFiled: November 20, 1991Date of Patent: December 31, 1996Assignee: Lucent Technologies Inc.Inventors: Miron Abramovici, Vishwani D. Agrawal, Kwang-Ting Cheng, Krishna B. Rajan
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Patent number: 5499249Abstract: Testing of a sequential circuit (10) containing at least one embedded RAM (16) is accomplished by first generating a set of sequential vectors and then applying the vectors in sequence to a set of primary circuit inputs (PO.sub.o -PO.sub.j). The vectors are generated such that upon application to the circuit, the vectors excite potential faults at nodes (A) upstream of the RAM and propagate the effects of the faults through the RAM to the primary circuit outputs (PO.sub.o -PO.sub.j). Also, the test vectors serve to excite faults downstream of the RAM by propagating values through the RAM needed to excite the downstream faults. The fault effects (if any) that propagate to the circuit primary outputs are compared to a set of reference values to determine if any faults are present.Type: GrantFiled: May 31, 1994Date of Patent: March 12, 1996Assignee: AT&T Corp.Inventors: Vishwani D. Agrawal, Tapan J. Chakraborty
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Patent number: 5365528Abstract: To detect a delay fault along a signal path of interest (12) in a sequential digital circuit (10), a source flip-flop (14) and a destination flip-flop (16), proximate the beginning and end of the path, respectively, are designated in the circuit. Next, the signal path is activated to establish what logic values are necessary at the input of each of a set of combinational elements (18.sub.1 -18.sub.p) in the path to propagate a selected signal transition from the source flip-flop to the destination flip-flop. A first and second backward justification process is carried out to synthesize a first sequence to propagate a selected logic value from a primary circuit input to the source flip-flop to cause it to generate the selected signal transition to propagate to the destination flip-flop. A second backward justification process is carried out to synthesize a second vector sequence which serves to propagate the value latched in the destination flip-flop to a primary output.Type: GrantFiled: April 3, 1992Date of Patent: November 15, 1994Assignee: AT&T Bell LaboratoriesInventors: Vishwani D. Agrawal, Tapan J. Chakraborty
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Patent number: 5257268Abstract: A method for developing a test sequence and for testing manufactured digital circuits. Test vectors are developed based on a simulation-based, directed-search approach. Specifically, from a given test vector, a next test vector is developed by altering the given test vector and determining the utility of the altered trial vector in propagating circuit faults to the primary outputs, based on a simulation of the circuit and a preselected cost function. The vector set is created through an iterative process of altering an accepted test vestor to develop a next trial vector. The vector set is efficiently developed by employing one phase that treats the entire set of circuit faults as the target, followed by another phase that targets specific faults that have not been detected in the previous phase.Type: GrantFiled: March 22, 1990Date of Patent: October 26, 1993Assignee: AT&T Bell LaboratoriesInventors: Prathima Agrawal, Vishwani D. Agrawal, Kwang T. Cheng
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Patent number: 5228040Abstract: A testable implementation of a given finite state machine is produced by defining a test finite state machine which can set and read the same number of flip flops as are required for the memory elements of the given finite machine and then merging the test finite state machine with the given finite state machine to produce a testable finite state machine in which the test finite state machine and the given finite state machine share the flip flops. The testable implementation is then produced from the testable finite state machine. Since the test finite state machine and the given finite state machine share the flip flops of the testable implementation, the test finite state machine can be used to test the given finite state machine by setting and reading the given finite state machine's flip flops. Techniques are further disclosed for defining the test finite state machine and merging the test finite state machine with the given finite state machine.Type: GrantFiled: March 9, 1990Date of Patent: July 13, 1993Assignee: AT&T Bell LaboratoriesInventors: Vishwani D. Agrawal, Kwang-Ting Cheng
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Patent number: 5043986Abstract: A method of partial scan design for chip testing and a circuit produced in accordance with the method in which the selection of scan memory elements eliminates cycles in the circuit while the circuit is in a test mode. Cycles are defined as feedback paths from an output of a memory element to an input of the memory element. Cycle length is the number of memory elements in a feedback path. Experimental data suggests that test complexity grows exponentially with the cycle length. By eliminating cycles of desired lengths, the set of scan memory elements may be only a small fraction of the total memory elements of a circuit.Type: GrantFiled: May 18, 1989Date of Patent: August 27, 1991Assignee: AT&T Bell LaboratoriesInventors: Vishwani D. Agrawal, Kwang-Ting Cheng
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Patent number: 4493077Abstract: A large scale sequential integrated circuit is made amenable to scan design testing by the inclusion of special multiplexing and storage circuits which respond to a pair of test control pulses to reconfigure the circuit to include one or more shift registers and to step the scan test data through the shift registers. In particular, the pair of test control pulses are applied to the two terminals to which, in normal operation, are applied the clock pulses which are used to control the storage elements and which, in such operation, are never both simultaneously high. To initiate the scan test operation, these test control pulses are made simultaneously high and the circuitry responds to such conditions.Type: GrantFiled: September 9, 1982Date of Patent: January 8, 1985Assignee: AT&T LaboratoriesInventors: Vishwani D. Agrawal, Melvin R. Mercer