Abstract: The rate limiter circuits in the packet processing chip of a NIC are a limited hardware resource that may limit the number of workloads that can be run on a server. Some such chips include an egress packet processing pipeline circuit and a second packet processing pipeline circuit that prepares work for the egress pipeline circuit. Some of the stages of the second pipeline circuit can be configured as a first limiter and a second limiter that implement aspects of different rate limiters such as IOPS limiters, bandwidth limiters, etc. Another pipeline stage can use the outputs of the different rate limiters to make a limiting decision that is written into one of the rate limiter circuits. The second pipeline circuit is thereby implementing virtualized rate limiters where one of the rate limiter circuits performs the rate limiting for the virtualized rate limiters.

Abstract: The rate limiter circuits in the packet processing chip of a NIC are a limited hardware resource that may limit the number of workloads that can be run on a server. Some such chips include an egress packet processing pipeline circuit and a second packet processing pipeline circuit that prepares work for the egress pipeline circuit. Some of the stages of the second pipeline circuit can be configured as a first limiter and a second limiter that implement aspects of different rate limiters such as IOPS limiters, bandwidth limiters, etc. Another pipeline stage can use the outputs of the different rate limiters to make a limiting decision that is written into one of the rate limiter circuits. The second pipeline circuit is thereby implementing virtualized rate limiters where one of the rate limiter circuits performs the rate limiting for the virtualized rate limiters.

Abstract: The throughput of a network appliance can be increased by a circuit that produces an encrypted block and a digest value while requiring only a single read of a data block. Data blocks, including a first data block, are stored in a memory that can be accessed by an ASIC that includes an encryption offload circuit. The ASIC can read the first data block from the memory and the encryption offload circuit can produce a first encrypted block and a first digest value from the first data block. The ASIC can produce a network packet that includes the first encrypted block and a data digest value. The first digest value is used to produce the data digest value, and a single read of the first data block from the memory is performed for producing the first encrypted block and also for calculating the first digest value.

Abstract: InfiniBand transport protocol today supports RDMA operations such as read and write with each operation having an opcode defined in the InfiniBand standard. Currently, new RDMA operations require extending the transport protocol by defining a new opcode, its respective header and enhancing InfiniBand implementations to support this new behavior. A more robust way of extending RDMA without requiring an expanding set of opcodes is to register computer code by associating it with a code key similar to a memory key. An InfiniBand channel adapter receiving an RDMA request that includes a code key executes the associated computer code, perhaps compiling it first, in response to receiving the RDMA request. The RDMA response returned to the requester includes an execution result indicating an outcome of executing the executable computer code.

Abstract: The InfiniBand transport protocol supports the concept of a SRQ (shared receive queue) by which multiple QPs (queue pairs) can share the same receive queue resources. According to the InfiniBand Specification, when a SRQ is enabled, flow control needs to be disabled. The lack of flow control mechanism results in there being no fairness guarantees across multiple requesters. Fairness across requesters can be obtained by implementing a SRQ configured to receive request messages from requesters initiating transactions that consume WQEs (work queue elements) of the SRQ, monitoring consumption of the WQEs by the requesters, determining that a requester has a WQE consumption exceeding a policing threshold, and in response to determining that the WQE consumption of the requester exceeds the policing threshold, sending a response message to the requester that results in reducing the WQE consumption of the requester.

Abstract: Virtual functions (VFs) running on SR-IOV (single root IO virtualization) capable PCIe devices can migrate in association with VMs using the VFs. A SR-IOV capable PCIe device installed in a host computer can implement the VFs. A VM running on the host and associated with the VF can use the VF to obtain a service such as network communications or access to a NAS device. Migrating the VF in association with the VM can include halting the VM in a VM state on the host, halting the VF in a PCIe state and then obtaining a PCIe state data, restarting the VF in the PCIe state on a second PCIe device of a second host based on the PCIe state data, and restarting the VM in the VM state on the second host, wherein the VM is configured to use the VF on the second PCIe device.

Abstract: A multitude of data transfer queues can have data transfer operations that are scheduled for a processing circuit to perform. Some of the data transfer queues may submit so many or such large data transfer operations that others receive little or no attention. The situation can be resolved in the data plane via a processing circuit that performs the data transfer operations in conjunction with priority evaluation operations that can assign the data transfer queues to different scheduler priority classes. A scheduler can schedule data transfer operations based on the scheduler priority classes of the data transfer queues.

Abstract: Load balancing of NVMe targets based on real time metrics can be obtained for NAS appliances mirroring a namespace by assigning the NAS appliances to service sets that include an active load balancing set, a monitored inactive set, and an out of service set. Storage performance metrics of the NAS appliances can be tracked by monitoring IO operations for accessing a NAS mirroring the namespace in a non-volatile memory. Based on the storage metrics, NAS appliances can be moved from one of the service sets to another. Dummy IO operations can be used to track the storage performance metrics of monitored inactive NAS appliances such that a monitored inactive NAS may be moved to the active load balancing set when certain performance constraints are met.

Abstract: Increased fairness for small vs large NVMe IO commands for accessing a non-volatile memory namespace provided by a network attached storage appliance can be realized by placing NVMe submissions received by a NVMe SQ on a first fabric queue set or a second fabric queue set based on a fairness policy. The first fabric queue set accesses the namespace via a first fabric connection. The second fabric queue set accesses the namespace via a second fabric connection. Accessing the namespace via the fabric connections results in NVMe completions that are merged from the fabric queue sets onto an NVMe completion queue. A process producing the NVMe submissions and receiving the resulting NVMe completions may be unaware of the multiple fabric queue sets.