Abstract: Disclosed are methods, systems, and non-transitory computer-readable medium for distributed vehicle processing. For instance, the method may include: in response to determining a first trigger condition of a first set of trigger conditions is satisfied, performing a first process corresponding to the first trigger condition on-board a vehicle; in response to determining a second trigger condition of a second set of trigger conditions is satisfied, prompting a second process corresponding to the second trigger condition by transmitting an edge request to an edge node and receiving an edge response from the edge node; and in response to determining a third trigger condition of a third set of trigger conditions is satisfied, prompting a third process corresponding to the third trigger condition by transmitting a cloud request to a cloud node and receiving a cloud response from the cloud node.

Abstract: Disclosed are methods, systems, and non-transitory computer-readable medium for distributed vehicle processing. For instance, the method may include: in response to determining a first trigger condition of a first set of trigger conditions is satisfied, performing a first process corresponding to the first trigger condition on-board a vehicle; in response to determining a second trigger condition of a second set of trigger conditions is satisfied, prompting a second process corresponding to the second trigger condition by transmitting an edge request to an edge node and receiving an edge response from the edge node; and in response to determining a third trigger condition of a third set of trigger conditions is satisfied, prompting a third process corresponding to the third trigger condition by transmitting a cloud request to a cloud node and receiving a cloud response from the cloud node.

Abstract: Disclosed is a method, a computer program product and a device that includes a receiver for receiving a downlink signal transmitted into a cell. The receiver is operable to obtain time, carrier frequency and cell-specific preamble synchronization to the received signal and includes a plurality of synchronization units that include a first detector to detect a frame boundary using preamble delay correlation; a second detector to detect the frame boundary with greater precision using a conjugate symmetry property over a region identified by the first detector; a cyclic prefix correlator to resolve symbol boundary repetition; an estimator, using the cyclic prefix, to estimate and correct a fractional carrier frequency offset; an operator to perform a Fast Fourier Transform of an identified preamble symbol and a frequency domain cross-correlator to identify cell-specific preamble sequences and an integer frequency offset in sub-carrier spacing.

Abstract: Disclosed is a method, a computer program product and a device that includes a receiver for receiving a downlink signal transmitted into a cell. The receiver is operable to obtain time, carrier frequency and cell-specific preamble synchronization to the received signal and includes a plurality of synchronization units that include a first detector to detect a frame boundary using preamble delay correlation; a second detector to detect the frame boundary with greater precision using a conjugate symmetry property over a region identified by the first detector; a cyclic prefix correlator to resolve symbol boundary repetition; an estimator, using the cyclic prefix, to estimate and correct a fractional carrier frequency offset; an operator to perform a Fast Fourier Transform of an identified preamble symbol and a frequency domain cross-correlator to identify cell-specific preamble sequences and an integer frequency offset in sub-carrier spacing.

Abstract: An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements include an iterative decoder element capable of calculating, for one or more iterations or one or more layers of the parity-check matrix processed during at least one iteration, a check-to-variable message based upon a first minimum magnitude and a second minimum magnitude of a plurality of variable-to-check messages for a previous iteration or layer, and a sign value associated with a plurality of variable-to-check messages for the previous iteration or layer. In this regard, the first and second minimum magnitudes and the sign value can be read from a check-to-variable message memory.

Abstract: An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements can include a permuter and/or de-permuter capable of permuting and/or depermuting, for at least one iteration or at least one layer of the parity-check matrix, at least one data array. The permuter/de-permuter can include a permuting Benes network and a sorting Benes network. In this regard, the permuting Benes network can include a plurality of switches for permuting the LLR for the previous iteration or layer, or de-permuting the portion of the LLR for the iteration or layer. Driving the permuting Benes network, then, the sorting Benes network can be capable of generating control logic for the switches of the permuting Benes network.

Abstract: An error correction decoder for block serial pipelined layered decoding of block codes includes a plurality of elements capable of processing, for at least one of a plurality of iterations of an iterative decoding technique, at least one layer of a parity check matrix. The elements include an iterative decoder element capable of calculating, for one or more iterations or one or more layers of the parity-check matrix, a check-to-variable message. Calculating the check-to-variable message can include calculating a magnitude of the check-to-variable message based upon a first minimum magnitude, a second minimum magnitude and a third minimum magnitude of a plurality of variable-to-check messages for a previous iteration or layer.

Abstract: An error correction decoder for block serial pipelined layered decoding of block codes includes primary and mirror memories that are each capable of storing log-likelihood ratios (LLRs) for one or more iterations of an iterative decoding technique. The decoder also includes a plurality of elements capable of processing, for one or more iterations, one or more layers of a parity-check matrix. The elements include an iterative decoder element capable of calculating, for one or more iterations or layers, a LLR adjustment based upon the LLR for a previous iteration/layer, the LLR for the previous iteration/layer being read from the primary memory. The decoder further includes a summation element capable of reading the LLR for the previous iteration/layer from the mirror memory, and calculating the LLR for the iteration/layer based upon the LLR adjustment for the iteration/layer and the previous iteration/layer LLR for the previous iteration/layer.