Patents by Inventor Vishwas Tumkur Vijayendra

Vishwas Tumkur Vijayendra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Smart diagnosis of integrated circuits including IP cores with encrypted simulation models
    Patent number: 10216877
    Abstract: The present embodiments relate to methods for simulating the behavior of an IP core that has an encrypted simulation model. The encrypted simulation model of the IP core may include a plurality of probes, which a debug option may activate selectively, if desired. The encrypted simulation model may collect data during a simulation as selected by the activated probes of the plurality of probes. The encrypted simulation model may perform smart diagnosis of the collected data based on a set of rules and generate feedback messages that may suggest corrective action in the event of a simulation failure.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 26, 2019
    Assignee: Altera Corporation
    Inventors: Vishwas Tumkur Vijayendra, Bo Zhou
  • Method and apparatus for performing a single pass compilation for systems with dynamically reconfigurable logic blocks
    Patent number: 10102172
    Abstract: A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.
    Type: Grant
    Filed: December 27, 2015
    Date of Patent: October 16, 2018
    Assignee: Altera Corporation
    Inventors: Kevin W. Mai, Vishwas Tumkur Vijayendra, Jakob Raymond Jones
  • SMART DIAGNOSIS OF INTEGRATED CIRCUITS INCLUDING IP CORES WITH ENCRYPTED SIMULATION MODELS
    Publication number: 20180089352
    Abstract: The present embodiments relate to methods for simulating the behavior of an IP core that has an encrypted simulation model. The encrypted simulation model of the IP core may include a plurality of probes, which a debug option may activate selectively, if desired. The encrypted simulation model may collect data during a simulation as selected by the activated probes of the plurality of probes. The encrypted simulation model may perform smart diagnosis of the collected data based on a set of rules and generate feedback messages that may suggest corrective action in the event of a simulation failure.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Applicant: Altera Corporation
    Inventors: Vishwas Tumkur Vijayendra, Bo Zhou