Patents by Inventor Vishwesh M. Rudramuni
Vishwesh M. Rudramuni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768533Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: August 2, 2022Date of Patent: September 26, 2023Assignee: Tahoe Research, Ltd.Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20230004209Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: August 2, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 11422615Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: January 13, 2020Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20200272219Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: January 13, 2020Publication date: August 27, 2020Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10564705Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: May 18, 2018Date of Patent: February 18, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20180364792Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: May 18, 2018Publication date: December 20, 2018Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10007323Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: December 23, 2013Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 9829963Abstract: Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.Type: GrantFiled: December 26, 2014Date of Patent: November 28, 2017Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nithish Mahalingam, Rushikesh S. Kadam, Vishwesh M. Rudramuni, Sujith Thomas
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Patent number: 9552039Abstract: Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that controls which specific core(s) are to be powered up/down and/or which power state these core(s) need to enter based, at least in part, on input from OS and/or software application(s). Other embodiments are also claimed and disclosed.Type: GrantFiled: September 27, 2012Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Rajeev Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni
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Patent number: 9207994Abstract: Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.Type: GrantFiled: May 9, 2012Date of Patent: December 8, 2015Assignee: Intel CorporationInventors: Harinarayanan Seshadri, Rajeev Muralidhar, Vishwesh M. Rudramuni, Illyas Mansoor
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Patent number: 9152218Abstract: Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.Type: GrantFiled: March 25, 2011Date of Patent: October 6, 2015Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nithish Mahalingam, Rushikesh S. Kadam, Vishwesh M. Rudramuni, Sujith Thomas
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Patent number: 9141179Abstract: A system and method of managing power may include determining a power state based on a first power management request from a first operating system executing on a mobile platform and a second power management request from a second operating system executing on the mobile platform. The first operating system and one or more components of the mobile platform can define a first virtual machine, and the second operating system and one or more components of the mobile platform can define a second virtual machine. In addition, the power state may be applied to the mobile platform.Type: GrantFiled: December 22, 2010Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Srividya Karumuri, Nithish Mahalingam, Vishwesh M. Rudramuni, Sujith Thomas, Rushikesh S. Kadam
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Publication number: 20150121114Abstract: Systems and methods of managing power in a computing platform may involve monitoring a runtime power consumption of two or more of a plurality of hardware components in the platform to obtain a plurality of runtime power determinations. The method can also include exposing one or more of the plurality of runtime power determinations to an operating system associated with the platform.Type: ApplicationFiled: December 26, 2014Publication date: April 30, 2015Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nithish Mahalingam, Rushikesh S. Kadam, Vishwesh M. Rudramuni, Sujith Thomas
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Patent number: 8775836Abstract: Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment.Type: GrantFiled: March 29, 2011Date of Patent: July 8, 2014Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Bruce L. Fleming, Vishwesh M. Rudramuni
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Publication number: 20140181560Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: December 23, 2013Publication date: June 26, 2014Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20140115368Abstract: Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that controls which specific core(s) are to be powered up/down and/or which power state these core(s) need to enter based, at least in part, on input from OS and/or software application(s). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: September 27, 2012Publication date: April 24, 2014Inventors: Rajeev Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni
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Patent number: 8601304Abstract: Techniques to tie a processor power state transition on a platform to another power state transition on the platform. In an embodiment, processor governor functionality of an operating system detects an idle condition of a processor executing the operating system. Based on the processor idle condition and one or more indicated conditions of other platform devices, tying logic may determine a system power state to transition the platform to. For example, the tying logic may select from one of a plurality of idle standby system power states.Type: GrantFiled: March 31, 2011Date of Patent: December 3, 2013Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Bruce L. Fleming, Vishwesh M. Rudramuni
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Publication number: 20130318379Abstract: Embodiments of apparatus, computer-implemented methods, computing devices, systems, and computer-readable media (transitory and non-transitory) are described herein for scheduling a plurality of tasks among a plurality of processor cores. A first processor core of a plurality of processor cores of a computing device may be transitioned to a shielded state, in which no new tasks are to be assigned to the first processor core and tasks already assigned to the first processor core are executed to completion, in response to a determination that a criterion has been met. In various embodiments, the criterion may be based on a condition of the computing device, such as power available to the computing device or a temperature associated with the computing device. In various embodiments, the first processor core may transition to a reduced-power state after the tasks already assigned to the first processor core execute completion.Type: ApplicationFiled: May 9, 2012Publication date: November 28, 2013Inventors: Harinarayanan Seshadri, Rajeev Muralidhar, Vishwesh M. Rudramuni, Illyas Mansoor
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Publication number: 20120166843Abstract: Techniques to tie a processor power state transition on a platform to another power state transition on the platform. In an embodiment, processor governor functionality of an operating system detects an idle condition of a processor executing the operating system. Based on the processor idle condition and one or more indicated conditions of other platform devices, tying logic may determine a system power state to transition the platform to. For example, the tying logic may select from one of a plurality of idle standby system power states.Type: ApplicationFiled: March 31, 2011Publication date: June 28, 2012Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Bruce L. Fleming, Vishwesh M. Rudramuni
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Publication number: 20120166779Abstract: Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment.Type: ApplicationFiled: March 29, 2011Publication date: June 28, 2012Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Bruce L. Fleming, Vishwesh M. Rudramuni