Patents by Inventor Vispi Cassod

Vispi Cassod has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220319171
    Abstract: In one embodiment, a video analytics system includes a camera network for capturing one or more videos and an EVA (electronic video analytics) platform, coupled to the camera network, operable to perform one or more of video aggregation, encryption, storage and analysis. The EVA platform has a content store for storing videos of the one or more captured videos, an event detection engine for defining one or more events that are each assigned a unique key when encountered in a video of the one or more captured videos, an aggregator for aggregating event-containing videos, and a renderer for rendering the event-containing videos.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 6, 2022
    Inventors: Mohammad Darwish, Paul Russell, Vispi Cassod, Hassan Sawaf
  • Patent number: 7724684
    Abstract: A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19).
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: May 25, 2010
    Assignee: Modelware, Inc.
    Inventors: Vispi Cassod, Anthony Dalleggio, Amine Kandalaft
  • Publication number: 20080291917
    Abstract: A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19).
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Inventors: Vispi Cassod, Anthony Dalleggio, Amine Kandalaft