Patents by Inventor Visvesh Sathe

Visvesh Sathe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10938397
    Abstract: Examples of recording channels and methods for biopotential signal acquisition and/or recording are described. Recording channels described herein may implement any combination of techniques described herein including multiplexing of multiple electrode inputs, delta encoding of biopotential signals, and common mode suppression.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: March 2, 2021
    Assignee: University of Washington
    Inventors: William Anthony Smith, Visvesh Sathe
  • Publication number: 20200266824
    Abstract: Examples of recording channels and methods for biopotential signal acquisition and/or recording are described. Recording channels described herein may implement any combination of techniques described herein including multiplexing of multiple electrode inputs, delta encoding of biopotential signals, and common mode suppression.
    Type: Application
    Filed: November 3, 2017
    Publication date: August 20, 2020
    Applicant: University of Washington
    Inventors: William Anthony Smith, Visvesh Sathe
  • Patent number: 8289063
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: October 16, 2012
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Publication number: 20120187991
    Abstract: A clock frequency of a clock signal used by a processor may be temporarily reduced to compensate for voltage droops in the power supply to the processor. A device may include a multiplexer to receive a group of phase shifted versions of the clock signal and to output one of the group of phase shifted versions of the clock signal as an output clock signal. A control component may receive the output clock signal from the multiplexer and a voltage droop event signal indicating whether a voltage droop event is occurring in a power supply. The control component may control, in response to the voltage droop event signal indicating the occurrence of the voltage droop event, the multiplexer to iteratively select the group of phase shifted versions of the clock signal to reduce the frequency of the output clock signal.
    Type: Application
    Filed: January 25, 2011
    Publication date: July 26, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Visvesh SATHE, Samuel NAFFZIGER, Sanjay PANT
  • Publication number: 20110215854
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Application
    Filed: May 18, 2011
    Publication date: September 8, 2011
    Applicant: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Patent number: 7956664
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: June 7, 2011
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Patent number: 7719316
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: May 18, 2010
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Patent number: 7719317
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: May 18, 2010
    Assignee: The Regents of the University of Michigan
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Publication number: 20080303552
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains includes a respective clock generator driven by the reference clock to generate a resonant clock signal, respective circuitry coupled to the clock generator to operate in accordance with the resonant clock signal, with the circuitry including a capacitive load for the resonant clock signal and a respective inductance coupled to the circuitry and the clock generator to resonate the capacitive load of the circuitry.
    Type: Application
    Filed: December 3, 2007
    Publication date: December 11, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Publication number: 20080303576
    Abstract: Disclosed herein is a digital system that includes a distribution network to carry a reference clock, and a circuit domain coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. The circuit domain includes a clock generator driven by the reference clock to generate a resonant clock signal, an input port to receive a control signal, and a gate coupled to the input port to discontinue application of the resonant clock signal within the circuit domain based on the control signal.
    Type: Application
    Filed: December 3, 2007
    Publication date: December 11, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou
  • Publication number: 20080150605
    Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.
    Type: Application
    Filed: December 3, 2007
    Publication date: June 26, 2008
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Juang-Ying Chueh, Jerry Kao, Visvesh Sathe, Marios C. Papaefthymiou, Conrad Ziesler
  • Publication number: 20060082387
    Abstract: A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.
    Type: Application
    Filed: June 15, 2005
    Publication date: April 20, 2006
    Inventors: Marios Papaefthymiou, Visvesh Sathe, Conrad Ziesler