Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: The apparatus of present invention converts AC or DC power sources to AC or DC power loads, in a single stage, bidirectionally, employing variable, high frequency resonant circuits and power switches, to continuously vary the gain of the conversion circuit. Inrush current control, idle converter turn off, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down, and dimming operation are inherent characteristics of the apparatus of the instant invention. A remotely configurable and operable controller may optionally be used to control the mode of conversion, the amplitude and frequency of the output voltages. The resonant circuits can be paralleled to derive multiple outputs. Multiple converter stages can be cascaded to meet the various power needs of an application such as multiple outputs and different amplitudes. Components can be eliminated for specific conversion applications. The circuits can be implemented in semiconductor packages.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: The present invention is directed to Bidirectional Multimode Power Converter which employs a high frequency dynamically varying amplitude modulation and voltage steering method to convert the source AC or DC voltages to output AC or DC voltages, with programmable output voltage levels, output voltage frequency and duration. The inrush current control, turning off the idle converter, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down of converter, dimming operation modes are inherent characteristics of the Bidirectional Multimode power converter. The Bidirectional Multimode Power Converters of the present invention facilitates bidirectional conversion and coupling multiple bidirectional sources and or loads. The Bidirectional Multimode Power Converter of the present invention supports local and remote control for changing operational characteristics of the converter on demand or on a programmed time of the day for a specified duration of time.

Abstract: A fault tolerant, multi-protocol shelf management controller architecture that is extensible provides an intelligent platform management interface that is version indifferent as well as programmable and reconfigurable. The shelf management controller is arranged in a dual redundant configuration in a client-server mode and has a message driven configuration with the messages conforming to the Intelligent Platform Management Interface (IPMI) specification as extended by PICMG 3.0. In one embodiment, each shelf management controller includes at least one bit stream processor comprising sequenced stage machines implementing one or more finite state machines associated with one or more devices that are under control of the shelf management controller. The finite state machines could be hardware or software based. The shelf management controller is also modeled as a layered architecture that includes an IPMI API layer.

Abstract: A modular chassis arrangement for electronic modules that is configurable into a mechanically and electrically interconnected structure capable of delivering scalable mechanical, electrical and environmental functionality for a multiplicity of electronic modules. In one embodiment, the electronic modules are compliant with AdvancedTCA or MicroTCA standards in a modular Pico-Shelf configuration that support stackable and/or back-to-back multiple unit chassis.

Abstract: A standard compliant printed circuit base boards or modules for telecommunications, networking and computer equipment electrically and mechanically couples with reusable modular daughter cards to provide application-specific functionality within spatial limitations as required to comply with industry specifications. In particular, an Advanced Mezzanine Card (AMC) Specification compliant printed circuit board is configured for releseably coupling with one or more reusable daughter cards to provide reconfigurable, modularized and scalable electrical functionality in an AMC form factor.