Abstract: The present invention is directed to Bidirectional Multimode Power Converter which employs a high frequency dynamically varying amplitude modulation and voltage steering method to convert the source AC or DC voltages to output AC or DC voltages with programmable output voltage levels, output voltage frequency and duration. The Bidirectional Multimode Power Converters of the present invention support: inrush current control, turning off the idle converter, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down of converter, dimming operation, programmable time of the day operation and operation for specified duration of time. The Bidirectional Multimode Power Converters of the present invention support coupling of multiple power sources for bidirectional power conversion.

Abstract: The present invention is directed to Bidirectional Multimode Power Converter which employs a high frequency dynamically varying amplitude modulation and voltage steering method to convert the source AC or DC voltages to output AC or DC voltages with programmable output voltage levels, output voltage frequency and duration. The Bidirectional Multimode Power Converters of the present invention support: inrush current control, turning off the idle converter, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down of converter, dimming operation, programmable time of the day operation and operation for specified duration of time. The Bidirectional Multimode Power Converters of the present invention support coupling of multiple power sources for bidirectional power conversion.

Abstract: The present invention is directed to Bidirectional Multimode Power Converter which employs a high frequency dynamically varying amplitude modulation and voltage steering-method to convert the source AC or DC voltages to output AC or DC voltages with programmable output voltage levels, output voltage frequency and duration. The Bidirectional Multimode Power Converters of the present invention support: inrush current control, turning off the idle converter, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down of converter, dimming operation, programmable time of the day operation and operation for specified duration of time. The Bidirectional Multimode Power Converters of the present invention support coupling of multiple power sources for bidirectional power conversion.

Abstract: An enhanced Ethernet protocol for computing and telecommunication supports a shortened frame size for communicating data payloads among selected devices within a constrained neighborhood based on a unique identification.

Abstract: The present invention is directed to Bidirectional Multimode Power Converter which employs a high frequency dynamically varying amplitude modulation and voltage steering method to convert the source AC or DC voltages to output AC or DC voltages, with programmable output voltage levels, output voltage frequency and duration. The inrush current control, turning off the idle converter, line voltage brown out protection, soft start, high pre-charge voltage generation, soft shut down of converter, dimming operation modes are inherent characteristics of the Bidirectional Multimode power converter. The Bidirectional Multimode Power Converters of the present invention facilitates bidirectional conversion and coupling multiple bidirectional sources and or loads. The Bidirectional Multimode Power Converter of the present invention supports local and remote control for changing operational characteristics of the converter on demand or on a programmed time of the day for a specified duration of time.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: An enhanced Ethernet protocol for computing and telecommunication supports a shortened frame size for communicating data payloads among selected devices within a constrained neighborhood based on a unique identification.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: An enhanced Ethernet protocol for computing and telecommunication supports a shortened frame size for communicating data payloads among selected devices within a constrained neighborhood based on a unique identification.