Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.

Abstract: A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.

Abstract: A standards-based server blade arrangement is provided wherein individual circuit boards may be compliant with a first industry driven or other standard and housed within an enclosure configured such that one aspect of the enclosure provides each circuit board with a scalable, mechanical, electrical and environmental functionality required for that circuit board to comply with the first industry driven or other standard and a second aspect of the enclosure allows the enclosure to comply with a second industry driven or other standard.

Abstract: A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

Abstract: A cage that is received with a Personal Computer (PC) enclosure in the same manner a peripheral can be received within the PC. The cage is provided with fans, circuitry, connectors and structural features to create a ATCA or MicroTCA type environment required for the operation of an AMC card. The cage features a lateral connector for connecting to the motherboard and transferring PCI-Express protocolized signals between the cage and the CPU. The cage also features means to receive and support an AMC card within the ATCA and MicroTCA environment created for it by the cage. In this configuration, the CPU can communicate with the AMC card using the PCI-Express interconnect protocol as if the AMC card is another peripheral I/O device. In this manner, an advanced form factor AMC card may be tested and used within a PC environment suitable only for conventional form factor expansion cards and peripheral I/O devices.

Abstract: A voltage level range based redundant power supply architecture is described wherein at least two power supplies are connected to an external load and maintained in an energized state. However, only one of the power supplies sources all the current requirements of the load while the other power supply remains in standby mode. This is achieved by manually or programmatically adjusting the voltage output of a first power supply and a second power supply connected in parallel to the external load such that the first power supply always outputs a higher potential difference at the point of load than the second power supply, thereby implementing a voltage level range of outputs of the power supplies so as to guarantee that all the current requirement of the load is sourced from the first power supply. The second power supply remains energized and upon failure of the first power supply instantaneously takes over the function of the failed power supply and powers the load.

Abstract: An enhanced Ethernet protocol for computing and telecommunication supports a shortened frame size for communicating data payloads among selected devices within a constrained neighborhood based on a unique identification.

Abstract: A computing and communication architecture utilizes a serial protocol based switched fabric among circuit cards housed in packaging arrangement. In one embodiment, each circuit card connected to the serial protocol based switched fabric in the packaging arrangement is provided with a protocol processor that enables all of the circuit cards to efficiently provide packet-based serial self-clocked communications at line speed. As a result, it is not necessary to arrange the circuit cards in a hierarchical manner in order to address the problems of switch blocking and related traffic congestion issues that would otherwise limit the implementation of the serial protocol based backplane arrangement for housing circuit cards.

Abstract: A modular chassis arrangement for electronic modules that is configurable into a mechanically and electrically interconnected structure capable of delivering scalable mechanical, electrical and environmental functionality for a multiplicity of electronic modules. In one embodiment, the electronic modules are compliant with AdvancedTCA or MicroTCA standards in a modular Pico-Shelf configuration that support stackable and/or back-to-back multiple unit chassis.

Abstract: A fault tolerant, multi-protocol shelf management controller architecture that is extensible provides an intelligent platform management interface that is version indifferent as well as programmable and reconfigurable. The shelf management controller is arranged in a dual redundant configuration in a client-server mode and has a message driven configuration with the messages conforming to the Intelligent Platform Management Interface (IPMI) specification as extended by PICMG 3.0. In one embodiment, each shelf management controller includes at least one bit stream processor comprising sequenced stage machines implementing one or more finite state machines associated with one or more devices that are under control of the shelf management controller. The finite state machines could be hardware or software based. The shelf management controller is also modeled as a layered architecture that includes an IPMI API layer.

Abstract: A reconfigurable, protocol indifferent bit stream-processing engine, and related systems and data communication methodologies, are adapted to achieve the goal of providing inter-fabric interoperability among high-speed networks operating a speeds of at least 10 gigabits per second. The bit-stream processing engine operates as an omni-protocol, multi-stage processor that can be configured with appropriate switches and related network elements to create a seamless network fabric that permits interoperability not only among existing communication protocols, but also with the ability to accommodate future communication protocols. The method and systems of the present invention are applicable to networks that include storage networks, communication networks and processor networks.

Abstract: A simple network comprises of: xDSL service equipment located at a distribution center coupled to an Aggregator Separator (AGSEP) System located at a DC; AGSEP system at the DC is coupled, using a high-speed link, to another AGSEP system located at a remote site, which is coupled to subscriber equipment using drop cables. The AGSEP systems aggregate the xDSL signals originating at either DC xDSL equipment or subscriber equipment, are carried over the high-speed link. The AGSEP systems and separate the aggregated signals at either end to distribute the separated signal to the respective equipment.

Abstract: A simple network comprises of: xDSL service equipment located at a distribution center coupled to an Aggregator Separator (AGSEP) System located at a DC; AGSEP system at the DC is coupled, using a high-speed link, to another AGSEP system located at a remote site, which is coupled to subscriber equipment using drop cables. The AGSEP systems aggregate the xDSL signals originating at either DC xDSL equipment or subscriber equipment, are carried over the high-speed link. The AGSEP systems and separate the aggregated signals at either end to distribute the separated signal to the respective equipment.

Abstract: Methods for broadband multimedia telecommunication include broadcasting a large selection of video streams via fiber optic to local switches which are coupled to customers by POTS lines and providing video streams, high QOS voice and VDSL data service from the local switch to customer premises. Signals from customer premises equipment communicate to the local switch to select up to four simultaneous video streams (out of hundreds available). According to the presently preferred embodiment, video, data, and digital voice service are provided via ATM cells to the local switch where they are multiplexed with lifeline POTS service and transmitted to the customer premises via ATM cells Multicast video streams are duplicated at the point in the switch closest to the customer.

Abstract: A network system includes a plurality of integrated access devices (IADs) assigned to a plurality of clients in a multi-client unit (MCU). At least one IAD is assigned to each of the plurality of clients in the multi-client unit to transmit and receives units of information. The IADs is configured to prioritize data transmission according to the type of information included in the units of information. An MCU gateway device is assigned to the multi-client unit and coupled to the plurality of IADs to receive or transmit the units of information. The gateway device is configured to prioritize the units of information according to the type of information included in the units of information. A regional switching device is assigned to a geographic region including the MCU.