Abstract: An Integrated Circuit (IC) includes an electronic circuit and a controller. The electronic circuit is designed to operate at temperatures above a specified minimal temperature. The IC has a controllable operational parameter that affects a performance measure of the electronic circuit and an amount of heat produced by the electronic circuit. The controller is configured to control the operational parameter so as to meet both requirements concurrently: (i) exceeding a specified minimal performance level of the performance measure, and (ii) a local temperature of the electronic circuit exceeding the specified minimal temperature.

Abstract: A physical layer transceiver, for connecting a host device to a wireline channel medium in which a signal component occurring at a particular time may cause interference at other times, includes a host interface for coupling to a host device, a line interface for coupling to the channel medium, and filter circuitry operatively coupled to the line interface to filter the interference caused by the signal component at the particular time and at the one or more other times. The filter circuitry includes at least one filter segment configured to operate at a first rate derived from a channel operating frequency to filter the signal component at the particular time, and at least one respective filter segment configured to operate at a respective additional rate different from the first rate. Respective delay elements allow each respective filter segment to filter the signal component at a one of the other times.

Abstract: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.

Abstract: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.