Patents by Inventor Viswanath Annampedu

Viswanath Annampedu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120197920
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits including a pattern detection circuit having at least two data detector circuits each operable to receive the same series of data samples and to provide a first detected data output and a second detected data output, respectively. In addition, the data pattern detection circuit includes a result combining circuit that is operable to assert a pattern found output based at least in part on the first detected data output and the second detected data output.
    Type: Application
    Filed: January 27, 2011
    Publication date: August 2, 2012
    Inventor: Viswanath Annampedu
  • Publication number: 20120182643
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier circuit, an analog to digital conversion circuit, a cosine component calculation circuit, a sine calculation circuit, and a zero gain start calculation circuit. The variable gain amplifier circuit is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The analog to digital conversion circuit is operable to convert the amplified output to a corresponding series of digital samples. The cosine component calculation circuit is operable to calculate a cosine component from the series of digital samples, and the sine component calculation circuit operable to calculate a sine component from the series of digital samples.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Inventors: Xun Zhang, Jeffrey Grundvig, Viswanath Annampedu
  • Publication number: 20120155587
    Abstract: Various embodiments of the present invention provide systems and methods for timing recovery. As an example, timing recovery circuits include: a first digital interpolation circuit, a second digital interpolation circuit, a phase selection circuit, and a sampling clock rotation circuit. The first digital interpolation circuit is operable to receive a data input and to provide a first interpolated output corresponding to a first phase, and the second digital interpolation circuit is operable to receive the data input and to provide a second interpolated output corresponding to a second phase. The phase selection circuit operable to select the first phase for processing, and the sampling clock rotation circuit is operable to move a sampling clock away from the first phase.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Inventor: Viswanath Annampedu
  • Patent number: 8199422
    Abstract: Methods and apparatus are provided for gain estimation using servo data with improved bias correction. The gain is estimated using a preamble in a servo sector by obtaining a first gain estimate using a first gain estimation algorithm (such as a Zero Gain Start Algorithm) and a first portion of the preamble; storing the first portion of the preamble in a memory buffer; obtaining a second gain estimate using a second gain estimation algorithm (such as a Zero Forcing algorithm) and the first portion of the preamble; and processing Servo Address Mark (SAM) and Gray data in the servo sector using the first gain estimate substantially simultaneous to the step of obtaining the second gain estimate. A gain error can be obtained by calculating a difference between the first gain estimate and the second gain estimate. The gain error can be used in burst processing of the servo data.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: June 12, 2012
    Assignee: LSI Corporation
    Inventors: Viswanath Annampedu, Xun Zhang
  • Publication number: 20120134042
    Abstract: Various embodiments of the present invention provide systems and methods for determining head polarity. As an example, a head polarity detection circuit includes: a first computation circuit, a second computation circuit, and an inversion determination circuit. The first computation circuit is operable to sum an absolute value of each sample of a first subset of a series of data samples corresponding to a first phase of an analog input to yield a first sum, and the second computation circuit is operable to sum an absolute value of each sample of a second subset of the series of data samples corresponding to a second phase of the analog input to yield a second sum. The first phase is more than ninety degrees offset from the second phase.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Inventors: Viswanath Annampedu, Jeffrey P. Grundvig, Keith R. Bloss, Vishal Narielwala
  • Publication number: 20120134043
    Abstract: Various embodiments of the present invention provide systems and methods for determining a location of a spiral pattern. As an example, a location detection circuits is discussed that includes: a pattern detection circuit, a computation circuit, and a center determination circuit. The pattern detection circuit is operable to identify a subset of a series of data samples corresponding to a defined pattern, and to indicate a location of the identified subset of the series of data samples. The series of data samples corresponds to a spiral pattern. The computation circuit operable to sum an absolute value of each sample of the subset of the series of data samples to yield a sum. The center determination circuit operable to identify a location of the spiral pattern using the sum.
    Type: Application
    Filed: November 29, 2010
    Publication date: May 31, 2012
    Inventors: Viswanath Annampedu, Jeffrey P. Grundvig, Keith R. Bloss, Vishal Narielwala
  • Publication number: 20120036173
    Abstract: Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first correlator value corresponding to a first binary transition to yield a first value; multiplying the portion of the series of data samples by a second correlator value corresponding to a second binary transition to yield a second value; adding the first value to a prior state value to yield a first interim value; adding the second value to the prior state value to yield a second interim value; and selecting the larger of the first interim value and the second interim value to yield a surviving interim value.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 9, 2012
    Inventor: Viswanath Annampedu
  • Publication number: 20120026620
    Abstract: Methods and apparatus are provided for gain estimation using servo data with improved bias correction. The gain is estimated using a preamble in a servo sector by obtaining a first gain estimate using a first gain estimation algorithm (such as a Zero Gain Start Algorithm) and a first portion of the preamble; storing the first portion of the preamble in a memory buffer; obtaining a second gain estimate using a second gain estimation algorithm (such as a Zero Forcing algorithm) and the first portion of the preamble; and processing Servo Address Mark (SAM) and Gray data in the servo sector using the first gain estimate substantially simultaneous to the step of obtaining the second gain estimate. A gain error can be obtained by calculating a difference between the first gain estimate and the second gain estimate. The gain error can be used in burst processing of the servo data.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 2, 2012
    Inventors: Viswanath Annampedu, Xun Zhang
  • Patent number: 8059349
    Abstract: Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: November 15, 2011
    Assignee: Agere Systems Inc.
    Inventors: Viswanath Annampedu, Keith R. Bloss, Tianyang Ding, Jeffrey P. Grundvig, Roy S. Neville
  • Patent number: 8054931
    Abstract: Various embodiments of the present invention provide systems and methods for improved timing recovery. As one example, some embodiments of the present invention provide timing recovery circuits that include an error signal and a digital phase lock loop circuit. The error signal indicates a difference between the predicted sample time and an ideal sample time. The digital phase lock loop is operable to apply an adjustment value such that a subsequent sample time is moved toward the ideal sample time. Further, the digital phase lock loop circuit includes an adjustment limit circuit that is operable to limit the adjustment value.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: November 8, 2011
    Assignee: Agere Systems Inc.
    Inventor: Viswanath Annampedu
  • Patent number: 8054573
    Abstract: Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium (278), and a SAM based fly-height adjustment circuit (214). The storage medium (278) includes a plurality of servo data regions (110) that each include a servo address mark (154). The SAM based fly-height adjustment circuit (214) receives the servo address mark (154) from the plurality of servo data regions (110) via the read/write head assembly (276), and calculates a first harmonics ratio (445) based on the received data. The first harmonics ratio (445) is compared with a second harmonics ratio (450) to determine an error (365) in the distance (295) between the read/write head assembly (276) and the storage medium (278).
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: November 8, 2011
    Assignee: LSI Corporation
    Inventors: George Mathew, Yuan Xing Lee, Hongwei Song, Jeffrey P. Grundvig, Viswanath Annampedu
  • Patent number: 8049982
    Abstract: Methods and apparatus are provided for measuring servo address mark distance in a read channel using selective fine phase estimates. A distance between servo address marks (SAMs) in servo data of a magnetic recording media can be computed by obtaining a count of a number of time intervals between SAM patterns; obtaining a plurality of fractional phase estimates; selecting at least one of the plurality of fractional phase estimates as a selected fractional phase estimate based on a selection criteria; and combining the count and the selected fractional phase estimate to compute the distance. The fractional phase estimates can include a first fractional phase estimate having a lower resolution and higher accuracy in the presence of frequency errors relative to a second fractional phase estimate and wherein the second fractional phase estimate has more resolution and lower accuracy in the presence of the frequency errors relative to the first fractional phase estimate.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: November 1, 2011
    Assignee: LSI Corporation
    Inventors: Jeffrey P. Grundvig, Viswanath Annampedu, Xun Zhang
  • Publication number: 20110157737
    Abstract: Various embodiments of the present invention provide systems and methods for locating a reference pattern on a storage medium. For example, various embodiments of the present invention provide systems for locating a reference pattern on a storage medium. Such systems include a sliding window phase calculator circuit, a delay circuit and a mark detector circuit.
    Type: Application
    Filed: December 31, 2009
    Publication date: June 30, 2011
    Inventors: Jeffrey Grundvig, Viswanath Annampedu, Jason Byrne, Keith Bloss
  • Publication number: 20110043938
    Abstract: Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium.
    Type: Application
    Filed: October 27, 2008
    Publication date: February 24, 2011
    Inventors: George Mathew, Yuan Xing Lee, Hongwei Song, Jeffrey P. Grundvig, Viswanath Annampedu
  • Patent number: 7813065
    Abstract: Various embodiments of the present invention provide systems and methods for performing modified rate burst demodulation. For example, a method for performing modified rate burst demodulation is disclosed. The method includes receiving a data input that includes a synchronization pattern, an information pattern, and a demodulation pattern. A periodic boundary is established along with a phase and frequency of a sampling clock based at least in part on the synchronization pattern. The information pattern is processed using the sampling clock to determine a location fix. The sampling clock is phase shifted by a skew amount and a phase shifted sampling clock is provided. The demodulation pattern is processed using the phase shifted sampling clock.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: October 12, 2010
    Assignee: Agere Systems Inc.
    Inventors: Viswanath Annampedu, Venkatram Muddhasani, Xun Zhang
  • Publication number: 20100232046
    Abstract: Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.
    Type: Application
    Filed: April 30, 2010
    Publication date: September 16, 2010
    Inventors: Viswanath Annampedu, Keith R. Bloss, Tianyang Ding, Jeffrey P. Grundvig, Roy S. Neville
  • Patent number: 7768437
    Abstract: Various embodiments of the present invention provide systems and methods for utilizing a plurality of potentially mismatched analog to digital converters. For example, a method for adaptively processing a variety of input signals is disclosed. The method includes providing an adaptive loop circuit, and a first and second circuit pairs. The first circuit pair includes a first analog to digital converter and first register, and the second circuit pair includes a second analog to digital converter and a second register. An input signal is received and an event status is received. The event status initially indicates that the input signal includes data associated with a first event and subsequently indicates that the input signal includes data associated with a second event. The first circuit pair to drive the adaptive loop circuit when the first event is indicated, and the second circuit pair to drive the adaptive circuit when the second event is indicated.
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: August 3, 2010
    Assignee: Agere Systems Inc.
    Inventors: Viswanath Annampedu, Venkatram Muddhasani
  • Publication number: 20100177430
    Abstract: Various embodiments of the present invention provide systems and methods for determining fly-height adjustments. For example, various embodiments of the present invention provide storage devices that include a storage medium, a read/write head assembly disposed in relation to the storage medium (278), and a SAM based fly-height adjustment circuit (214). The storage medium (278) includes a plurality of servo data regions (110) that each include a servo address mark (154). The SAM based fly-height adjustment circuit (214) receives the servo address mark (154) from the plurality of servo data regions (110) via the read/write head assembly (276), and calculates a first harmonics ratio (445) based on the received data. The first harmonics ratio (445) is compared with a second harmonics ratio (450) to determine an error (365) in the distance (295) between the read/write head assembly (276) and the storage medium (278).
    Type: Application
    Filed: October 27, 2008
    Publication date: July 15, 2010
    Inventors: George Mathew, Yuan Xing Lee, Hongwei Song, Jeffrey P. Grundvig, Viswanath Annampedu
  • Patent number: 7738200
    Abstract: Various systems and methods for peak signal detection. As one example, a method for peak signal detection that includes receiving a signal is disclosed. The received signal includes a signal region where the signal is increasing in amplitude, another signal region where the signal is decreasing in amplitude, and a transitional signal region coupling the first two signal regions. In some cases, the transitional region is of zero duration and the signal transitions directly from the increasing region to the decreasing region. The method further include calculating a distance between the signal region of increasing amplitude and the signal region of decreasing amplitude, and determining a peak of the received signal that is one half the distance from the signal region of increasing amplitude.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: June 15, 2010
    Assignee: Agere Systems Inc.
    Inventors: Viswanath Annampedu, Keith R. Bloss, Tianyang Ding, Jeffrey P. Grundvig, Roy S. Neville
  • Publication number: 20100142078
    Abstract: Various embodiments of the present invention provide systems and methods for low overhead disk wobble compensation. As an example, a method for performing synchronous wobble compensation processing is disclosed. The method includes providing a medium that includes a servo data region and a user data region. The servo data region includes a clock recovery pattern and a location pattern. A detectable pattern is written to the user data region a known number of bit periods from the location pattern. The detectable pattern is read back, and a fractional processing delay is calculated. Based at least on the fractional processing delay and a known number of bit periods from the location pattern to the end of the servo data region, a wobble compensation pattern is written an integral number of bit periods from the location pattern.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 10, 2010
    Inventors: Viswanath Annampedu, Terence Karanink, Xun Zhang, Jeffrey P. Grundvig