Patents by Inventor Viswanath Valluri

Viswanath Valluri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packaging substrate comprising staggered vias
    Patent number: 6538307
    Abstract: A packaging substrate is formed with staggered vias interconnecting fan-out circuitry for improved strength and rigidity. Embodiments of the present invention include substrates wherein less than 20% of the vias are aligned.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: March 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Viswanath Valluri, Edwin Fontecha, Melissa Siow Lui Lee
  • Micro-BGA beam lead connection with cantilevered beam leads
    Patent number: 6515354
    Abstract: A tape automated bonding (TAB) tape is provided with an insulating tape having a die receiving section. The TAB tape also has a conductive wiring pattern forming a plurality of traces including a land at one end and a beam lead at another end. A tape window is formed in a portion of the tape die receiving section. At least one trace beam lead extends over the tape window from a first direction and is connected to a tie bar adjacent an opposing side of the tape window and at least one trace beam lead extends over the tape window from a second direction different than the first direction and is cantilevered over the tape window.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Edwin R. Fontecha, Viswanath Valluri, Valerie Vivares
  • Cu-balanced substrate
    Patent number: 6507100
    Abstract: A packaging substrate is formed with electrically non-functional areas of Cu on the upper surface and/or lower surface for improved strength and rigidity and reduced warpage and bending. Embodiments of the present invention include substrates containing electrically non-functional grid-like Cu areas on the upper and lower surface such that the ratio of the total Cu area on one surface is about 55% to about 100% of the total Cu area on the other surface.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: January 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Viswanath Valluri, Edwin Fontecha, Melissa Siow-Lui Lee
  • Micro-BGA beam lead connection
    Patent number: 6465745
    Abstract: A semiconductor package is provided including a die bearing a plurality of bonding pads and a substrate connected to the die by a connecting agent, the substrate including a plurality of conductive traces forming a wiring pattern, a plurality of vias forming a matrix, and an opening at a position corresponding to the plurality of bonding pads. A plurality of conductive elements fill the vias and at least one trace electrically connected to a conductively filled via disposed adjacent a first side of the tape window is routed to a second side of the tape window to form a beam lead projecting into the tape window from the second side. The beam lead is electrically connected to one of the bonding pads.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: October 15, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Edwin R. Fontacha, Viswanath Valluri
  • Solder mask for controlling resin bleed
    Patent number: 6448507
    Abstract: Damage to and short circuiting of bond fingers on a substrate due to die-attach resin bleed is prevented, thereby increasing yield and improving reliability. Embodiments include forming a trough in a solder mask on a substrate between the bond fingers and semiconductor chip to prevent the die-attach resin from reaching the bond fingers.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Edwin Fontecha, Viswanath Valluri, Donald Bottarini