Patents by Inventor Viswanathan Lakshmanan
Viswanathan Lakshmanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8046726Abstract: A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs and (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors.Type: GrantFiled: September 16, 2008Date of Patent: October 25, 2011Assignee: LSI CorporationInventors: Viswanathan Lakshmanan, Michael Josephides, Lisa M. Miller
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Patent number: 7853901Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.Type: GrantFiled: April 25, 2008Date of Patent: December 14, 2010Assignee: LSI CorporationInventors: Viswanathan Lakshmanan, Thomas R. O'Brien, Richard D. Blinne
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Patent number: 7829973Abstract: A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.Type: GrantFiled: August 23, 2007Date of Patent: November 9, 2010Assignee: LSI CorporationInventors: Richard T. Schultz, Thomas R. O'Brien, Viswanathan Lakshmanan, David M. Ratchkov, Stefan G. Block
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Publication number: 20100070936Abstract: A method of waiving verification failures is disclosed. The method generally includes the steps of (A) generating a plurality of circuit error files by performing a plurality of physical verifications on a plurality of circuit designs, the circuit error files containing a plurality of circuit errors of the circuit designs, (B) generating a system error file by performing an additional physical verification on a system design, the system error file containing a plurality of system errors of the system design, the system design incorporating the circuit designs, (C) generating a valid error file by removing the circuit errors from the system error file, the valid error file containing a plurality of valid errors comprising a subset of the system errors and (D) storing the valid error file in a recording medium.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Inventors: Viswanathan Lakshmanan, Michael Josephides, Lisa M. Miller
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Publication number: 20090271755Abstract: A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Applicant: LSI CORPORATIONInventors: Viswanathan Lakshmanan, Thomas R. O'Brien, Richard D. Blinne
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Publication number: 20090051006Abstract: A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.Type: ApplicationFiled: August 23, 2007Publication date: February 26, 2009Applicant: LSI CORPORATIONInventors: Richard T. Schultz, Thomas R. O'Brien, Viswanathan Lakshmanan, David M. Ratchkov, Stefan G. Block
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Patent number: 7480878Abstract: A method and system for validating selected layers of an integrated circuit design. A rundeck is edited to include IC layers and device structures of interest that may require validation. In some embodiments the IC layer of interest may include only metal. A layout versus schematic (LVS) comparison is performed using the edited rundeck and an error report is generated.Type: GrantFiled: December 29, 2005Date of Patent: January 20, 2009Assignee: LSI Logic CorportionInventors: Alan Lee Holesovsky, Viswanathan Lakshmanan, Brent Wray Acott
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Patent number: 7302654Abstract: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.Type: GrantFiled: October 29, 2004Date of Patent: November 27, 2007Assignee: LSI CorporationInventors: Viswanathan Lakshmanan, Michael Josephides, Richard D. Blinne
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Patent number: 7260803Abstract: A method and system for performing dummy metal insertion in design data for an integrated circuit is disclosed, wherein the design data includes dummy metal objects inserted by a dummy fill tool. After a portion of the design data is changed, a check is performed to determine whether any dummy metal objects intersect with any other objects in the design data. If so, the intersecting dummy metal objects are deleted from the design data, thereby avoiding having to rerun the dummy fill tool.Type: GrantFiled: October 10, 2003Date of Patent: August 21, 2007Assignee: LSI CorporationInventors: Viswanathan Lakshmanan, Richard Blinne, Vikram Shrowty, Lena Montecillo
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Publication number: 20070157140Abstract: A method, a computer program product, and an apparatus for performing a trimmed verification analysis comprising selecting layers of interest for a trimmed analysis, eliminating layer definitions for unselected layers to create a trimmed rundeck, and performing a layout versus schematic verification comparison to generate a trimmed error report for the selected layers of interest.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Alan Holesovsky, Viswanathan Lakshmanan, Brent Acott
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Patent number: 7231626Abstract: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.Type: GrantFiled: December 17, 2004Date of Patent: June 12, 2007Assignee: LSI CorporationInventors: Jason K. Hoff, Viswanathan Lakshmanan, Michael Josephides, Daniel W. Prevedel, Richard D. Blinne, Johathan P. Kuppinger
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Patent number: 7219317Abstract: A method and computer program product for verifying an incremental change to an integrated circuit design include receiving as input an integrated circuit design database and an engineering change order. Objects in the integrated circuit design database are identified and marked to indicate a current state of the integrated circuit design database. The engineering change order is applied to the integrated circuit design database, and the integrated circuit design database is analyzed to generate a list of incremental changes to the integrated circuit design database resulting from the engineering change order. Objects in the integrated circuit design database included in the list of incremental changes are identified and marked to distinguish objects in the integrated circuit design database that were changed from the current state. The marked integrated circuit design database distinguishing the objects that were changed from the current state is generated as output.Type: GrantFiled: April 19, 2004Date of Patent: May 15, 2007Assignee: LSI Logic CorporationInventors: Viswanathan Lakshmanan, Richard D. Blinne, Jonathan P. Kuppinger
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Patent number: 7149989Abstract: A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.Type: GrantFiled: September 22, 2004Date of Patent: December 12, 2006Assignee: LSI Logic CorporationInventors: Viswanathan Lakshmanan, Alan Holesovsky, Lisa M. Miller, Jonathan P. Kuppinger
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Patent number: 7107559Abstract: A method of partitioning an integrated circuit design for physical design verification includes steps of receiving as input a representation of an integrated circuit design having a number of physical design layers and a composite run deck specifying rule checks to be performed on the integrated circuit design. The composite run deck is partitioned into partitioned run decks so that the number of physical design layers referenced by each of the partitioned run decks is a minimum. The representation of the integrated circuit design is parsed to filter only the physical design layers required for each of the partitioned run decks into a filtered data deck for each of the partitioned run decks. The filtered data deck is generated as output for each of the partitioned run decks.Type: GrantFiled: October 29, 2003Date of Patent: September 12, 2006Assignee: LSI Logic CorporationInventors: Viswanathan Lakshmanan, Richard D. Blinne, Jonathan P. Kuppinger
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Publication number: 20060136855Abstract: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.Type: ApplicationFiled: December 17, 2004Publication date: June 22, 2006Inventors: Jason Hoff, Viswanathan Lakshmanan, Michael Josephides, Daniel Prevedel, Richard Blinne, Jonathan Kuppinger
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Patent number: 7051318Abstract: A system for generating an Open Library Architecture Delay and Power Calculation Module. The system includes a user interface for generating and submitting requests that specify configurations and types of memories for which Open Library Architecture Delay and Power Calculation Modules are needed. A server is configured to received the requests and produce Open Library Architecture Delay and Power Calculation Modules in response thereto.Type: GrantFiled: October 9, 2001Date of Patent: May 23, 2006Assignee: LSI Logic CorporationInventors: Viswanathan Lakshmanan, Cristian T. Crisan, Balaji Ekambaram, Eugene V. Anikin
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Publication number: 20060095883Abstract: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.Type: ApplicationFiled: October 29, 2004Publication date: May 4, 2006Inventors: Viswanathan Lakshmanan, Michael Josephides, Richard Blinne
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Publication number: 20060090144Abstract: A method and computer program product for automatically correcting errors in an integrated circuit design includes steps of: (a) performing a physical design validation of an integrated circuit design to verify compliance with a set of design rules; (b) generating a results database of design rule violations detected by the physical design validation; (c) identifying locations in the integrated circuit design from the results database for making design corrections according to a post-processing rule deck so that the locations of the design corrections comply with the set of design rules; and (d) implementing the design corrections in the integrated circuit design.Type: ApplicationFiled: October 27, 2004Publication date: April 27, 2006Inventors: Viswanathan Lakshmanan, Michael Josephides, Richard Blinne
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Publication number: 20060064656Abstract: A method and computer program product for early physical design validation and identification of texted metal short circuits in an integrated circuit design includes steps of: (a) receiving as input a representation of an integrated circuit design; (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to one of identifying texted metal short circuits in the integrated circuit design and power distribution and input/output cell placement in the integrated circuit design; and (d) performing a physical design validation on the integrated circuit design from the specific rule deck.Type: ApplicationFiled: September 22, 2004Publication date: March 23, 2006Inventors: Viswanathan Lakshmanan, Alan Holesovsky, Lisa Miller, Jonathan Kuppinger
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Patent number: 7007248Abstract: A tool and method for implementing engineering change orders. The tool and method provides that a change file is checked, equivalent engineering change orders are computed and applied to an active cell. The engineering change orders are registered with a pre-determined tool name, and it is detected and reported if another tool needs to be run to restore routing information. The active cell is not automatically saved after the engineering change orders are applied. Instead, a user must manually save the active cell after the tool is run. The tool can work with three different name spaces: Verilog, VHDL and Avant! Verilog.Type: GrantFiled: May 15, 2003Date of Patent: February 28, 2006Assignee: LSI Logic CorporationInventors: Richard Blinne, Viswanathan Lakshmanan, Venugopalan Pranesan