Patents by Inventor Viswanathan RAMANATHAN

Viswanathan RAMANATHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11335669
    Abstract: A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: May 17, 2022
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Patent number: 11101160
    Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 24, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Publication number: 20200243369
    Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Patent number: 10629468
    Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 21, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Publication number: 20200083202
    Abstract: A method of fabricating an electronics package includes forming a cavity in a first surface of a semiconductor substrate, forming one or more passive devices on the semiconductor substrate, forming a microelectromechanical device on a piezoelectric substrate, and bonding the semiconductor substrate to the piezoelectric substrate with the microelectromechanical device disposed within the cavity.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Patent number: 10483248
    Abstract: An electronics package includes a semiconductor substrate having one or more passive devices formed thereon and a cavity defined in a first surface thereof. A piezoelectric substrate is bonded to the semiconductor substrate and has a radio frequency (RF) filter formed thereon. The RF filter is disposed within the cavity defined in the semiconductor substrate.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: November 19, 2019
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Publication number: 20180277527
    Abstract: An electronics package includes a semiconductor substrate having one or more passive devices formed thereon and a cavity defined in a first surface thereof. A piezoelectric substrate is bonded to the semiconductor substrate and has a radio frequency (RF) filter formed thereon. The RF filter is disposed within the cavity defined in the semiconductor substrate.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 27, 2018
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Publication number: 20170236742
    Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.
    Type: Application
    Filed: February 10, 2017
    Publication date: August 17, 2017
    Inventors: Jiro Yota, Hong Shen, Viswanathan Ramanathan
  • Patent number: 9735249
    Abstract: Gate structures for semiconductor devices include a silicon nitride layer, an electron beam evaporated tantalum nitride layer disposed on the silicon nitride layer, a first electron beam evaporated titanium layer disposed on the tantalum nitride layer, an electron beam evaporated gold layer deposited on the first titanium layer, and a second electron beam evaporated titanium layer deposited on the gold layer.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 15, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Shiban Kishan Tiku, Viswanathan Ramanathan
  • Publication number: 20160329410
    Abstract: Gate structures for semiconductor devices include a silicon nitride layer, an electron beam evaporated tantalum nitride layer disposed on the silicon nitride layer, a first electron beam evaporated titanium layer disposed on the tantalum nitride layer, an electron beam evaporated gold layer deposited on the first titanium layer, and a second electron beam evaporated titanium layer deposited on the gold layer.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: Shiban Kishan TIKU, Viswanathan RAMANATHAN
  • Patent number: 9422621
    Abstract: Gate metallization structures and methods for semiconductor devices are disclosed, wherein a refractory metal barrier is implemented to provide performance improvements. Transistor devices are disclosed having a compound semiconductor substrate and an electron-beam evaporated gate structure including a layer of tantalum nitride (TaNx), a layer of titanium (Ti) and a layer of gold (Au).
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Shiban Kishan Tiku, Viswanathan Ramanathan
  • Publication number: 20150152543
    Abstract: Systems, devices and methods related to reactive evaporation of refractory materials. In some embodiments, a method for performing reactive evaporation can include positioning a volume of refractory material such as tantalum within an evaporation chamber and forming a vacuum environment therein. The method can further include providing a beam of electrons to the volume of refractory material to evaporate the refractory material into evaporated particles. The method can further include introducing a flow of reactive gas such as nitrogen into the evaporation chamber to allow at least some of the reactive gas to react with at least some of the evaporated particles of the refractory material. The flow of reactive gas can be selected such that a layer such as tantalum nitride formed on a substrate by deposition of the evaporated particles includes a range of a desirable property.
    Type: Application
    Filed: October 29, 2014
    Publication date: June 4, 2015
    Inventors: Shiban Kishan TIKU, Lam T. LUU, Richard S. BINGLE, Haiping HU, Hsiang-Chih SUN, Viswanathan RAMANATHAN
  • Publication number: 20150123169
    Abstract: Gate metallization structures and methods for semiconductor devices are disclosed, wherein a refractory metal barrier is implemented to provide performance improvements. Transistor devices are disclosed having a compound semiconductor substrate and an electron-beam evaporated gate structure including a layer of tantalum nitride (TaNx), a layer of titanium (Ti) and a layer of gold (Au).
    Type: Application
    Filed: October 29, 2014
    Publication date: May 7, 2015
    Inventors: Shiban Kishan TIKU, Viswanathan RAMANATHAN