Patents by Inventor Viswanathan Sundararaman

Viswanathan Sundararaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6586839
    Abstract: A conductive via pattern (110) between the uppermost metal interconnect layer (Mn) and next underlying metal interconnect layer (Mn−1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn and Mn−1). The conductive via layer (110) may, for example, comprise parallel rails (114) or a grid of cross-hatch rails (116). By spreading the stress concentration laterally, the conductive via layer (110) inhibits micro-cracking from stress applied to the bond pad (112).
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: July 1, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Michael F. Chisholm, Darvin R. Edwards, Gregory B. Hotchkiss, Reynaldo Rincon, Viswanathan Sundararaman
  • Publication number: 20020025417
    Abstract: A conductive via pattern (110) between the uppermost metal interconnect layer (Mn ) and next underlying metal interconnect layer (Mn−1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (Mn and Mn−1). The conductive via layer (110) may, for example, comprise parallel rails (114) or a grid of cross-hatch rails (116). By spreading the stress concentration laterally, the conductive via layer (110) inhibits micro-cracking from stress applied to the bond pad (112).
    Type: Application
    Filed: August 23, 2001
    Publication date: February 28, 2002
    Inventors: Michael F. Chisholm, Darvin R. Edwards, Gregory B. Hotchkiss, Reynaldo Rincon, Viswanathan Sundararaman