Patents by Inventor Vit JANIREK

Vit JANIREK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071775
    Abstract: In an example, a method of manufacturing a semiconductor device includes providing a semiconductor substrate comprising an unpolished CZ silicon substrate, a substrate upper side, and a substrate lower side opposite to the substrate upper side. The method includes first annealing the semiconductor substrate at a first temperature in an inert environment for a first time. The method includes second annealing the semiconductor substrate at a second temperature in a wet oxidation environment for a second time. The first annealing dissolves inner wall oxide in bulk region voids and the second annealing fills the voids with semiconductor interstitials. In some examples, the CZ silicon substrate is provided from a CZ ingot grown in the presence of a magnetic field and using continuous counter-doping. The method provides, among other things, a CZ silicon substrate with reduced crystal originated particle (COP) defects, reduced oxygen concentration, and reduced radial resistivity variation.
    Type: Application
    Filed: August 24, 2022
    Publication date: February 29, 2024
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: David LYSACEK, Jan HYBL, Dusan POSTULKA, Juraj JARINA, Vit JANIREK, Alexandra SENKOVA