Patents by Inventor Vitaly Lagoon

Vitaly Lagoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8560893
    Abstract: A method and system are provided for automatically generating executable system-level tests from an initial action or partially specified scenario by accumulating necessary complement actions and forming a set of constraints required by the initial action and the necessary complement actions. The set of constraints is solved by a constraint solving engine to provide an at least partial sequence of the actions and parameters thereto that satisfies the set of constraints. The sequence of actions that comply with the set of constraints are used to generate an executable system-level test code.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yoav Hollander, Efrat Gavish, Vitaly Lagoon, Matan Vax
  • Patent number: 7870523
    Abstract: The present invention provides a system and method for resolving a test generation problem involving constraint resolution problems where a verification environment includes constraints that are suitable for resolution using one type of solver for a first domain and other constraints that are suitable for resolution using a different solver in a second domain. The invention further comprises variables and, in instances where at least one variable is in each of the first and second domains, using these solvers to restrict the set of permissible values of variables to be consistent in multiple domains, preferably in all relevant domains. A constraint resolution problem is divided into clusters of constraints connected within a domain, and connected clusters of clusters that are connected through shared variables that are subject to constraints in more than one cluster.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: January 11, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Shlomi Uziel, Amos Noy, Vitaly Lagoon, Yael Kinderman, Amit Gal
  • Patent number: 7613973
    Abstract: A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly “solve” the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner. The language structure is particularly suitable for such operators as “[: ]”, “|”, “&”, “^”, “˜”, “>>” and “<<”.
    Type: Grant
    Filed: December 20, 2004
    Date of Patent: November 3, 2009
    Assignee: Cadence Design (Israel) II Ltd.
    Inventors: Vitaly Lagoon, Guy Baruch
  • Publication number: 20050203720
    Abstract: A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly “solve” the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner. The language structure is particularly suitable for such operators as “[: ]”, “|”, “&”, “{circumflex over (?)}”, “˜”, “>>” and “<<”.
    Type: Application
    Filed: December 20, 2004
    Publication date: September 15, 2005
    Inventors: Vitaly Lagoon, Guy Baruch
  • Patent number: 6918076
    Abstract: A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly “solve” the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner. The language structure is particularly suitable for such operators as “[:]”, “|”, “&”, “^”, “˜”, “>>” and “<<”.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: July 12, 2005
    Assignee: Verisity Ltd.
    Inventors: Vitaly Lagoon, Guy Barruch
  • Publication number: 20020049944
    Abstract: A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly “solve” the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner. The language structure is particularly suitable for such operators as“[:]”,“|”,“&”,“&Lgr;”,“˜”,“>>” and “<<”.
    Type: Application
    Filed: August 28, 2001
    Publication date: April 25, 2002
    Inventors: Vitaly Lagoon, Guy Barruch