Abstract: The present invention relates to a data buffer memory (104) and method for storing data in a data communications network, and to a data buffer system (100) comprising such a data buffer memory. The data buffer memory comprising a data section (104a?) comprising a number of memory pages (104a); and a package descriptor section (104b?) comprising a 5 number of package descriptors (104b); wherein at least one queue (103) of packets is stored in the data section (104a?) as an ordered set of packages, and wherein a package is an ordered set of packets.

Abstract: Aspects of the disclosure provide a method for communicating queue information. The method includes determining a queue state for each one of a plurality of queues at least partially based on respective queue length, selecting a queue with a greatest difference between the queue state of the queue and a last reported queue state of the queue, and reporting the queue state of the selected queue to at least one node.

Abstract: A distributed network device and method for policing a flow of traffic in the chassis switch in communication networks. The distributed network device incudes a first processor configured to perform an egress processing operation on data packets received from a plurality second processor units in the distributed network switch, the data packets being destined for a receiving device coupled to the distributed network switch. Further, the distributed network device includes a metering unit associated with the first processor, the meting unit configured to meter a flow of the data packets to the receiving device and output a metering result. Also, the distributed network device includes a message generator configured to communicate to the plurality of second processors in the distributed network device a notification message indicative of the metering result.

Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.

Abstract: There is provided a network device comprising a physical queue management processor configured to manage attributes of physical queues of data packets. The network device further comprises a scheduling processor which is configured to manage scheduling nodes that establish a scheduling hierarchy among the physical queues in a network, utilizing a bi-directional mapping of the physical queues to logical queues. The network device further comprises a traffic management processor which is configured to modify the bi-directional mapping mentioned above.

Abstract: A system and method for bypassing server CPU by redirecting data transactions between network and disk provides an innovative implementation for intercepting network to disk data traffic and performing transactions on this data using internal logic rather than a CPU, providing transparent functionality with improved performance as compared to conventional solutions. This is particularly useful in sending and receiving data blocks between network connections and disk storage, such as in distributed storage servers.

Abstract: A storage virtualization offload engine (SVOE) optimizes network storage stack applications, providing an innovative implementation for network storage event processing. The current embodiment is particularly suited for distributed storage servers, offloading storage related functions from CPU to a co-processor. The SVOE improves system performance and power consumption by executing heavy operations (such as wide vector computations) by dedicated hardware engines. Thus, the SVOE avoids the significant overhead and overall task latency of a CPU using system calls in the middle of software thread to offload processing. A system includes two or more event processing elements (EPEs). Each EPE is configured for receiving events that include respective tasks and for processing only data access portions of the tasks.

Abstract: A server receives requests as events from a client via a network. Each event includes a respective task that requires access to disk storage. The server includes one or more processors that process the tasks in a run-to-completion manner and two or more hardware engines to which the processor(s) offload(s) at least some of the processing of the tasks. The hardware engines perform computation-intensive operations such as table lookups and hashes. Preferably, if there are more than one processor, the processors are identical RISC-core event processing elements, all configured with identical instruction code for execution. Preferably, the server also includes a network interface card; the processor(s) and the hardware engines may be part of either the network interface card or a separate co-processor.

Abstract: An apparatus and method of bypassing server DRAM by redirecting internal data transactions to an embedded buffer provides an innovative implementation for intermediate storage for internal transactions, providing transparent functionality with improved performance as compared to conventional solutions. Transaction throughput is improved at least in part by avoiding using conventional DRAM, thus eliminating conventional bottlenecks in DRAM intermediate storage. The current embodiment is particularly useful in sending and receiving data blocks between disk storage and network connections.

Abstract: Static and dynamic power is saved in systems on a chip (SoCs) with an array of multiple RISC cores by adjusting power consumption using a combination of architecture and algorithm. Elements can be turned on and off with a higher granularity as compared to conventional implementations. An event distributor/power manager matches input queues queue occupancy to how many elements need to be active continuously to process incoming events without delaying event processing. Both instantaneous and average power can be controlled, in particular reduced to lower levels than in conventional systems while maintaining continuous processing of a varying level (number) of received events. Resulting power consumption is optimally tuned to the instantaneous workload. As compared to conventional solutions, the current implementation is a complex system approach taking into considerations multiple factors, and the algorithm can be implemented autonomously for more dynamic system re-configuration (than conventional solutions).

Abstract: A Software Enabled Network Storage Accelerator (SENSA) system includes a number of SENSA components. The components can be implemented individually or in combination for a variety of applications, in particular, data base acceleration, disk caching, and event stream processing applications. Hardware (HW) real time operating system (RTOS) optimization for network storage stack applications such as event processing avoids conventional CPU usage by processing the payload, or internal data, of a packet using an array of at least two event processing elements (EPEs), each EPE in the array configured for: receiving events, each of the events having a task corresponding to the event; and processing the task in run-to-completion manner by operating on some portions of the task and offloading other portions of the task.

Abstract: In a method of processing packets in a network, a packet is received at an ingress port of a network device. A traffic class associated with the packet is determined. Based on the traffic class, it is determined whether the packet should transmitted without being enqueued by a traffic manager of the network device. When it is determined that that the packet should be transmitted without being enqueued by the traffic manager, the packet is sent to an egress port of the network device without enqueuing the packet by the traffic manager. When it is determined that the packet should not be transmitted without being enqueued in the network device, the packet is enqueued in a queue in the traffic manager of the network device. The packet sent to the egress port without being enqueued by the traffic manager is accounted for in the traffic manager.

Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.

Abstract: Aspects of the disclosure provide a method for network traffic scheduling. The method includes selecting, at a present node within a node hierarchy that multiplexes a plurality of input nodes to an output node, a winning node from a plurality of lower level nodes, obtaining first parameters provided from the winning node, the first parameters being in association with the winning node, determining second parameters in association with the present node at least partially based on the first parameters, and providing the second parameters in association with the present node to an upper level node in the node hierarchy for scheduling at the upper level node. To determine the second parameters in association with the present node, in an embodiment, the method includes using the first parameters to look up an entry in a lookup table that stores the second parameters in association with the first parameters.

Abstract: Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation.

Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.

Abstract: The disclosed embodiments relate to a system for controlling accesses to one or more memory devices. This system includes one or more write queues configured to store entries for write requests, wherein a given entry for a write request includes an address and write data to be written to the address. The system also includes a search mechanism configured to receive a read request which includes an address, and to search the one or more write queues for an entry with a matching address. If a matching address is found in an entry in a write queue, the search mechanism is configured to retrieve the write data from the entry and to cancel the associated write request, whereby the read request can be satisfied without accessing the one or more memory devices.

Abstract: A method of and a network processor unit for processing of packets in a network, the network processor comprising: communication interface configured to receive and transmit packets; at least one processing means for processing packets or parts thereof; an embedded switch configured to switch packets between the communication interface and the processing means; and wherein the embedded switch is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means for processing thereof, to receive the processed first part of the packet from the processing means, and to transmit the processed first part of the packet.

Abstract: Embodiments of the present invention provide a system for scheduling memory accesses for one or more memory devices. This system includes a set of queues configured to store memory access requests, wherein each queue is associated with at least one memory bank or memory device in the one or more memory devices. The system also includes a set of hierarchical levels configured to select memory access requests from the set of queues to send to the one or more memory devices, wherein each level in the set of hierarchical levels is configured to perform a different selection operation.

Abstract: A method of and a network processor unit (10) for processing of packets in a network, the network processor (10) comprising: communication interface (14) configured to receive and transmit packets; at least one processing means (16) for processing packets or parts thereof; an embedded switch (12) configured to switch packets between the communication interface (14) and the processing means (16); and wherein the embedded switch (12) is configured to analyze a received packet and to determine whether the packet should be dropped or not; if the packet should not be dropped, the switch is configured to store the received packet, to send a first part of the packet to the processing means (16) for processing thereof, to receive the processed first part of the packet from the processing means (16), and to transmit the processed first part of the packet.