Patents by Inventor Vithal Rao

Vithal Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, system, and medium for asset-based permissions management for resellers of cloud exchange assets
    Patent number: 10878483
    Abstract: In general, this disclosure describes techniques for hierarchical management of co-location facility assets and permissions. For example, techniques are described for managing permissions for sub-customer access to reseller assets of a co-location facility, where the sub-customers are customers of the reseller. The techniques as described herein may, as a result, enable customers that become resellers to assign assets of the cloud exchange and manage sub-customer permissions to those assigned assets, including sub-customer orderings and/or access of assets associated with one or more geographically distinct co-location facilities and port-level assets.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: December 29, 2020
    Assignee: EQUINIX, INC.
    Inventors: Kirk Allan Felbinger, Robert Leighton Noakes, II, Suraj Prakash Dasika, Theodore James Wagner, Thomas Banola, Padmanabha Rao Rayadurga Vithal Rao
  • Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process
    Patent number: 8161355
    Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: April 17, 2012
    Assignee: MoSys, Inc.
    Inventors: Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee T. Chua, Jawji Chen, Kameswara K. Rao
  • Constant reference cell current generator for non-volatile memories
    Patent number: 7944281
    Abstract: A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (IREF).
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: May 17, 2011
    Assignee: MoSys, Inc.
    Inventors: Da-Guang Yu, Vithal Rao
  • Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process
    Publication number: 20100205504
    Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.
    Type: Application
    Filed: February 11, 2009
    Publication date: August 12, 2010
    Applicant: Mosys, Inc.
    Inventors: Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee T. Chua, Jawji Chen, Kameswara K. Rao
  • Constant Reference Cell Current Generator For Non-Volatile Memories
    Publication number: 20100148855
    Abstract: A reference current generation circuit generates a first branch current that varies by a first percentage in response to variations in a first supply voltage and variations in transistor threshold voltage. The first branch current is mirrored to create a corresponding second branch current. A first portion (sub-current) of the second branch current is supplied through a first transistor, which exhibits the transistor threshold voltage wherein the first sub-current varies by a second percentage in response to the variations in the first supply voltage and variations in transistor threshold voltage, wherein the second percentage is greater than the first percentage. A second portion (sub-current) of the second branch current is supplied through a second transistor. The second portion of the second branch current is mirrored to create a reference current (IREF).
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Applicant: MoSys,Inc.
    Inventors: Da-Guang Yu, Vithal Rao