Abstract: In accordance with one embodiment the subject of the patent is a method for storing a database comprising entity objects or data structures representing the data entities, and relationship objects or data structures representing the relationships amongst the entities. Each relationship object or data structure possesses links to the entity objects or data structures that play the various roles in the relationship. Where there is a link from a relationship to an entity, there is also a link from the entity to the relationship, facilitating queries and updates to the database system. It is possible and often desirable for an embodiment to permit not merely one, but possibly many (or zero) entities to play each role in a relationship. The database is value-oriented in the sense that the address of an entity is not part of the key, thus permitting value-comparison-based searches.

Abstract: Bit blocks for an adder are provided which include a first bit stage that generates a first bit associated propagation characteristic (bapc). The bapc is independent of a carry input to the bit block from another bit block of the adder. Additional bit stages may be included in the bit block such as a second bit stage that, based on the first bapc, generates a second bapc that is also independent of the carry input to the bit block. The first and second bapc may be generated based on first and second operand bits input to the respective stages and a bapc that is generated by a less significant bit stage of the bit block and is independent of the carry input to the bit block. Adders including the bit blocks and methods for adding using the bit block as well as bit block size optimization methods are also provided.

Abstract: Bit blocks for an adder are provided which include a first bit stage that generates a first bit associated propagation characteristic (bapc). The bapc is independent of a carry input to the bit block from another bit block of the adder. Additional bit stages may be included in the bit block such as a second bit stage that, based on the first bapc, generates a second bapc that is also independent of the carry input to the bit block. The first and second bapc may be generated based on first and second operand bits input to the respective stages and a bapc that is generated by a less significant bit stage of the bit block and is independent of the carry input to the bit block. Adders including the bit blocks and methods for adding using the bit block as well as bit block size optimization methods are also provided.

Abstract: A 64-bit precision digital circuit for computing the exponential function and a related 64-bit precision digital circuit for computing sine and cosine, each circuit comprising a master circuit and a slave circuit. The master circuit computes the remainders {tilde over (x)}i for every “logical” iteration i using fast, low-precision circuit, thereby accumulating temporary errors. Only at the end of every 8 i's, which marks the end of a “physical” iteration, is a complete and fast correction to the accumulated errors performed. The slave circuit computes quantities called the yi's, which will eventually converge to the desired output.

Abstract: An improved radix-4 CORDIC rotator iteration stage, using answer digits {−3, −1, 1, 3} instead of the conventional choices of {−3, −2, −1, 0,1, 2, 3} or {−2, −1, 0, 1, 2}, thereby achieving constant magnitude amplification. The invention includes an answer digit decision module, which normally examines only a few digits of the remainder angle &thgr;i−1, thereby saving time when compared to full-length comparison. Very rarely does the answer digit decision process involves examining close to all the digits of the remainder angle. When examining only a few digits of the remainder angle, the circuit takes only approximately 20% longer than a radix-2 CORDIC stage. The invented rotator stage is usable either as a pipeline stage or as a single-stage iterative circuit. For use in a pipeline, the invented stage is to be used only when only a few remainder angle bits need to be examined.

Abstract: A 64-bit precision digital circuit for computing the exponential function and a related 64-bit precision digital circuit for computing sine and cosine, each circuit comprising a master circuit and a slave circuit. The master circuit computes the remainders x.sub.i for every "logical" iteration i using fast, low-precision circuit, thereby accumulating temporary errors. Only at the end of every 8 i's, which marks the end of a "physical" iteration, is a complete and fast correction to the accumulated errors performed. The slave circuit computes quantities called the y.sub.i 's, which will eventually converge to the desired output.

Abstract: A carry-lookahead/carry-select binary adder includes a plurality of Manchester carry-lookahead cells arranged by length in monotonically increasing order at a first level and a carry-lookahead cell(s) at a second level connected to the first level cells. The cells generate corresponding groups of carry-propagate and carry-generate bits for respective portions of a first and a second binary operand to be summed. From each of the groups, a carry signal is derived for selecting the outputs of one of two parallel binary ripple adders. Based on the selection, the correct sum bits for respective portions of the first and a second binary operands are output. By arranging the first level cells in monotonically increasing order, the summation can occur quickly and each of the portions can be summed in a relatively uniform amount of time.